From 7db506c3dd70f9ac0e8cdc481a47fa3835538be2 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 2 Oct 2016 11:56:39 +0200 Subject: src/northbridge: Remove unnecessary whitespace Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/16851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/via/cx700/raminit.c | 4 ++-- src/northbridge/via/vx800/dev_init.c | 4 ++-- src/northbridge/via/vx800/drdy_bl.c | 12 ++++++------ src/northbridge/via/vx800/driving_clk_phase_data.h | 14 +++++++------- src/northbridge/via/vx800/freq_setting.c | 4 ++-- src/northbridge/via/vx900/pcie.c | 2 +- src/northbridge/via/vx900/raminit_ddr3.c | 10 +++++----- 7 files changed, 25 insertions(+), 25 deletions(-) (limited to 'src/northbridge/via') diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 14a17d4771..aad851d929 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -303,8 +303,8 @@ static const u8 Init_Rank_Reg_Table[] = { static const u16 DDR2_MRS_table[] = { /* CL: 2, 3, 4, 5 */ - 0x150, 0x1d0, 0x250, 0x2d0, /* BL = 4 ;Use 1X-bandwidth MA table to init DRAM */ - 0x158, 0x1d8, 0x258, 0x2d8, /* BL = 8 ;Use 1X-bandwidth MA table to init DRAM */ + 0x150, 0x1d0, 0x250, 0x2d0, /* BL = 4; Use 1X-bandwidth MA table to init DRAM */ + 0x158, 0x1d8, 0x258, 0x2d8, /* BL = 8; Use 1X-bandwidth MA table to init DRAM */ }; #define MRS_DDR2_TWR2 ((0 << 15) | (0 << 20) | (1 << 12)) diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index 7cd557a02c..7ac5fe1999 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -325,7 +325,7 @@ static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 }; // with 75 ohm // { DLL: reset. A11(MA8)=1 } // // DDR2 CL = 2 CL = 3 CL = 4 CL = 5 CL = 6(Burst type = interleave)(WR fine tune in code) -static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM +static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL = 4; Use 1X-bandwidth MA table to init DRAM // MA11 MA10(AP) MA9 #define CHA_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h @@ -534,7 +534,7 @@ static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; / // { DLL: reset. A11(MA8)=1 } // // DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code) -static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM +static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4; Use 1X-bandwidth MA table to init DRAM // MA11 MA10(AP) MA9 #define CHB_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c index b9466b9813..0c5f63c2d4 100644 --- a/src/northbridge/via/vx800/drdy_bl.c +++ b/src/northbridge/via/vx800/drdy_bl.c @@ -304,7 +304,7 @@ static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] = {PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, 0x3f, 0x00, Rx54E3T, Rx55E3T}, // 200/200 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E1T, Rx55E1T}, // 200/266 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T} // 200/333 -// DDR2 Both E3T and E2T Fail, need set to E1T, db PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 00110011b, 00000000b, Rx54E3T, Rx55E3T ;200/266 +// DDR2 Both E3T and E2T Fail, need set to E1T, db PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 00110011b, 00000000b, Rx54E3T, Rx55E3T; 200/266 }, // cpu166 { @@ -326,7 +326,7 @@ static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] = }, // cpu333 { - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100 ;DO NOT Support + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100; DO NOT Support {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T}, // 333/133 {PH3_3_3_3, PH0_0_0_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54E0T, Rx55E0T}, // 333/166 {PH2_3_3_2, PH0_0_3_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x3f, 0x00, Rx54E1T, Rx55E1T}, // 333/200 @@ -348,7 +348,7 @@ static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = {PH1_0_0_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x06, 0x00, Rx54E3T, Rx55E3T}, // 100/133 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // 100/166 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // 100/200 - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // ;100/266 + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // 100/266 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T} // 100/333 }, // cpu133 @@ -380,7 +380,7 @@ static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = }, // cpu266 { - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 266/100 ;DO NOT Support + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 266/100; DO NOT Support {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T}, // 266/133 {PH2_2_1_2, PH0_0_0_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54E0T, Rx55E0T}, // 266/166 {PH3_3_3_3, PH0_0_3_3, PH0_0_0_0, PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, 0x3f, 0x00, Rx54E2T, Rx55E2T}, // 266/200 @@ -389,7 +389,7 @@ static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = }, // cpu333 { - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100 ;DO NOT Support + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100; DO NOT Support {PH3_3_3_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T}, // 333/133 {PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54L1T, Rx55L1T}, // 333/166 {PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x3f, 0x00, Rx54E1T, Rx55E1T}, // 333/200 @@ -568,7 +568,7 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) } } - /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL = 4 ; =1 BL = 8 */ + /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL = 4; =1 BL = 8 */ if (BL & 0x08) /*All Assembly support BL = 8 */ BL = 0x8; /*set bit3 */ diff --git a/src/northbridge/via/vx800/driving_clk_phase_data.h b/src/northbridge/via/vx800/driving_clk_phase_data.h index 08299c7a94..e9190fac30 100644 --- a/src/northbridge/via/vx800/driving_clk_phase_data.h +++ b/src/northbridge/via/vx800/driving_clk_phase_data.h @@ -16,14 +16,14 @@ #ifndef DRIVINGCLKPHASEDATA_H #define DRIVINGCLKPHASEDATA_H -//extern u8 DDR2_DQSA_Driving_Table[4] ; -//extern u8 DDR2_DQSB_Driving_Table[2] ; +//extern u8 DDR2_DQSA_Driving_Table[4]; +//extern u8 DDR2_DQSB_Driving_Table[2]; -//extern u8 DDR2_DQA_Driving_Table[4] ; -//extern u8 DDR2_DQB_Driving_Table[2] ; +//extern u8 DDR2_DQA_Driving_Table[4]; +//extern u8 DDR2_DQB_Driving_Table[2]; -//extern u8 DDR2_CSA_Driving_Table_x8[4] ; -//extern u8 DDR2_CSB_Driving_Table_x8[2] ; +//extern u8 DDR2_CSA_Driving_Table_x8[4]; +//extern u8 DDR2_CSB_Driving_Table_x8[2]; //extern u8 DDR2_CSA_Driving_Table_x16[4]; //extern u8 DDR2_CSB_Driving_Table_x16[2]; @@ -31,7 +31,7 @@ //extern u8 DDR2_MAA_Driving_Table[MA_Table][4]; //extern u8 DDR2_MAB_Driving_Table[MA_Table][2]; -//extern u8 DDR2_DCLKA_Driving_Table[4] ; +//extern u8 DDR2_DCLKA_Driving_Table[4]; //extern u8 DDR2_DCLKB_Driving_Table[4]; #define DUTY_CYCLE_FREQ_NUM 6 diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 6e11704e28..6592efdefd 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -135,7 +135,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) } if (!AllDimmSupportedCL) { /*if equal 0, no supported CL */ PRINT_DEBUG_MEM("SPD Data Error, Can not get CL !!!! \r"); - for (;;) ; + for (;;); } /*Get CL Value */ @@ -192,7 +192,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) if (CycTime <= 0) { //error! - for (;;) ; + for (;;); } /* cycle time value diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c index f717384e8f..ae81739185 100644 --- a/src/northbridge/via/vx900/pcie.c +++ b/src/northbridge/via/vx900/pcie.c @@ -52,7 +52,7 @@ static void vx900_pcie_link_init(device_t dev) /* Step 2: Wait for device to enter L0 state */ /* FIXME: implement timeout detection */ - while (0x8a != pci_read_config8(dev, 0x1c3)) ; + while (0x8a != pci_read_config8(dev, 0x1c3)); /* Step 3: Clear PCIe error status, then check for failures */ pci_write_config32(dev, 0x104, 0xffffffff); diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index f4b61de88b..aff62f2773 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -737,7 +737,7 @@ static void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom, printram("Hw MRS set is 0x%4x\n", reg16); pci_write_config16(MCU, 0xcc, reg16); /* Wait for MRS commands to be sent */ - while (pci_read_config8(MCU, 0xcc) & 1) ; + while (pci_read_config8(MCU, 0xcc) & 1); } /* @@ -1114,7 +1114,7 @@ static void vx900_rx_capture_range_calib(u8 pinswap) pci_write_config8(MCU, 0x71, reg8); /* Wait for it */ - while (pci_read_config8(MCU, 0x71) & 0x10) ; + while (pci_read_config8(MCU, 0x71) & 0x10); vx900_dram_exit_read_leveling(pinswap); } @@ -1146,7 +1146,7 @@ static void vx900_rx_dqs_delay_calib(u8 pinswap) pci_mod_config8(MCU, 0x71, 0x03, 0x02); /* Wait for calibration to complete */ - while (pci_read_config8(MCU, 0x71) & 0x02) ; + while (pci_read_config8(MCU, 0x71) & 0x02); vx900_dram_exit_read_leveling(pinswap); /* Restore the refresh counter */ @@ -1163,7 +1163,7 @@ static void vx900_tx_dqs_trigger_calib(u8 pattern) /* Trigger calibration */ pci_mod_config8(MCU, 0x75, 0, 0x20); /* Wait for calibration */ - while (pci_read_config8(MCU, 0x75) & 0x20) ; + while (pci_read_config8(MCU, 0x75) & 0x20); } /* @@ -1192,7 +1192,7 @@ static void vx900_tx_dq_delay_calib(void) /* Trigger calibration */ pci_mod_config8(MCU, 0x75, 0, 0x02); /* Wait for calibration */ - while (pci_read_config8(MCU, 0x75) & 0x02) ; + while (pci_read_config8(MCU, 0x75) & 0x02); } static void vx900_rxdqs_adjust(delay_range * dly) -- cgit v1.2.3