From 24d1d4b47274eb82893e6726472a991a36fce0aa Mon Sep 17 00:00:00 2001
From: Stefan Reinauer <reinauer@chromium.org>
Date: Thu, 21 Mar 2013 11:51:41 -0700
Subject: x86: Unify arch/io.h and arch/romcc_io.h

Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.

Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.

Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
---
 src/northbridge/via/cx700/early_serial.c      | 2 +-
 src/northbridge/via/vx800/early_serial.c      | 2 +-
 src/northbridge/via/vx800/examples/romstage.c | 1 -
 src/northbridge/via/vx800/pci_rawops.h        | 2 +-
 4 files changed, 3 insertions(+), 4 deletions(-)

(limited to 'src/northbridge/via')

diff --git a/src/northbridge/via/cx700/early_serial.c b/src/northbridge/via/cx700/early_serial.c
index cde0b31dc5..ae59295200 100644
--- a/src/northbridge/via/cx700/early_serial.c
+++ b/src/northbridge/via/cx700/early_serial.c
@@ -21,7 +21,7 @@
  * Enable the serial devices on the VIA CX700
  */
 
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 
 static void cx700_writepnpaddr(u8 val)
 {
diff --git a/src/northbridge/via/vx800/early_serial.c b/src/northbridge/via/vx800/early_serial.c
index b6f58ac580..b3ebde1433 100644
--- a/src/northbridge/via/vx800/early_serial.c
+++ b/src/northbridge/via/vx800/early_serial.c
@@ -20,7 +20,7 @@
 /*
  * Enable the serial devices on the VIA
  */
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 
 /* The base address is 0x15c, 0x2e, depending on config bytes */
 
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 228cc7e3cd..7c3fb7ae87 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "console/console.c"
 #include "lib/ramtest.c"
diff --git a/src/northbridge/via/vx800/pci_rawops.h b/src/northbridge/via/vx800/pci_rawops.h
index 8e775607bc..33eebc40ac 100644
--- a/src/northbridge/via/vx800/pci_rawops.h
+++ b/src/northbridge/via/vx800/pci_rawops.h
@@ -22,7 +22,7 @@
 #define NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H
 
 #include <stdint.h>
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 
 struct VIA_PCI_REG_INIT_TABLE {
 	u8 ChipRevisionStart;
-- 
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