From 7d31e7c13897e4b2548136c7a6f701b9121b7ad3 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Sat, 8 Jun 2013 11:49:10 -0500 Subject: VX900: Add DDR3 initialization The VX900 can be connected to either DDR2 or DDR3. On my board, it is DDR3, hence why there is no and will be no DDR2 code from my side. This is the raminit for DDR3 dimms for the VX900. I like the term "raminit" better than "memory training". This is a device, not a dog. What works and what doesn't is documented in the code. It does not make sense to hide that information in a commit message. Change-Id: Ib2ebc10e6d4d22d0a937fe9e895c17ce79153c88 Signed-off-by: Alexandru Gagniuc Reviewed-on: http://review.coreboot.org/3417 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/northbridge/via/vx900/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/via/vx900/Makefile.inc') diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index 3e0d9c7692..1586c87751 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -21,7 +21,7 @@ romstage-y += pci_util.c romstage-y += early_smbus.c romstage-y += early_vx900.c romstage-y += early_host_bus_ctl.c -#romstage-y += raminit_ddr3.c +romstage-y += raminit_ddr3.c romstage-y += ./../../../device/dram/ddr3.c romstage-y += ./../../../southbridge/via/common/early_smbus_delay.c romstage-y += ./../../../southbridge/via/common/early_smbus_is_busy.c -- cgit v1.2.3