From 14e22779625de673569c7b950ecc2753fb915b31 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 27 Apr 2010 06:56:47 +0000 Subject: Since some people disapprove of white space cleanups mixed in regular commits while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/via/vx800/driving_setting.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/via/vx800/driving_setting.c') diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c index c6a7edda05..bdba494d85 100644 --- a/src/northbridge/via/vx800/driving_setting.c +++ b/src/northbridge/via/vx800/driving_setting.c @@ -58,7 +58,7 @@ void DRAMDriving(DRAM_SYS_ATTR * DramAttr) /* ODT Control for DQ/DQS/CKE/SCMD/DCLKO in ChA & ChB which include driving enable/range and strong/weak selection - + Processing: According to DRAM frequency to ODT control bits. Because function enable bit must be the last one to be set. So the register VIA_NB3DRAM_REGD4 and VIA_NB3DRAM_REGD3 should be @@ -125,7 +125,7 @@ static const u8 ODTLookup_TBL[ODTLookup_Tbl_count][3] = { }; #define ODT_Table_Width_DDR2 4 -// RxD6 RxD3 +// RxD6 RxD3 static const u8 ODT_Control_DDR2[ODT_Table_Width_DDR2] = { 0xFC, 0x01 }; void DrivingODT(DRAM_SYS_ATTR * DramAttr) -- cgit v1.2.3