From 15279a9696c70b82c2223264a505da9122f9aa7b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 28 Jul 2016 21:05:26 +0200 Subject: src/northbridge: Capitalize CPU, RAM and ROM Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/via/cx700/lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/via/cx700') diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index ece05b10f3..2d7431628f 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -203,7 +203,7 @@ static void cx700_set_lpc_registers(struct device *dev) enables |= 1 << 3; pci_write_config8(dev, 0x4d, enables); - /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ + /* Set bit 3 of 0x4f to match award (use INIT# as CPU reset) */ enables = pci_read_config8(dev, 0x4f); enables |= 0x08; pci_write_config8(dev, 0x4f, enables); @@ -220,7 +220,7 @@ static void cx700_set_lpc_registers(struct device *dev) // Power management setup setup_pm(dev); - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + /* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */ pci_write_config8(dev, 0x40, 0x54); /* Enable HPET timer */ -- cgit v1.2.3