From ea7b518ec087ff7847ba2ff8b717305db4c14ab9 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Thu, 9 Oct 2008 17:08:32 +0000 Subject: Indent-based + manual cleanups for CN700 (trivial). As this will be ported to v3 sooner or later we cleanup _now_, so we don't have to do it twice. - Whitespace, coding style improvements. - Fix a few typos. - Add a missing #endif in raminit.h. - Drop an unused variable. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/via/cn700/agp.c | 76 +++++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 34 deletions(-) (limited to 'src/northbridge/via/cn700/agp.c') diff --git a/src/northbridge/via/cn700/agp.c b/src/northbridge/via/cn700/agp.c index 7158369cb3..6ae8e78361 100644 --- a/src/northbridge/via/cn700/agp.c +++ b/src/northbridge/via/cn700/agp.c @@ -32,24 +32,27 @@ static void agp_init(device_t dev) { u32 reg32; - - /* Some of this may not be necessary, - * it should be handled by the OS */ + + /* Some of this may not be necessary (should be handled by the OS). */ printk_debug("Enabling AGP.\n"); - - /* Allow R/W access to AGP registers */ + + /* Allow R/W access to AGP registers. */ pci_write_config8(dev, 0x4d, 0x15); - - /* Setup PCI latency timer */ + + /* Setup PCI latency timer. */ pci_write_config8(dev, 0xd, 0x8); - - /* Set to AGP 3.0 Mode, which should theoretically render the rest of - * the registers set here pointless */ + + /* + * Set to AGP 3.0 Mode, which should theoretically render the rest of + * the registers set here pointless. + */ pci_write_config8(dev, 0x84, 0xb); - + /* AGP Request Queue Size */ pci_write_config8(dev, 0x4a, 0x1f); - /* AGP Hardware Support (default 0xc4) + + /* + * AGP Hardware Support (default 0xc4) * 7: AGP SBA Enable (1 to Enable) * 6: AGP Enable * 5: Reserved @@ -57,25 +60,26 @@ static void agp_init(device_t dev) * 3: AGP8X Mode Enable * 2: AGP4X Mode Enable * 1: AGP2X Mode Enable - * 0: AGP1X Mode Enable */ + * 0: AGP1X Mode Enable + */ pci_write_config8(dev, 0x4b, 0xc4); - + /* Enable AGP Backdoor */ pci_write_config8(dev, 0xb5, 0x03); - - /* Set aperture to 32MB */ - /* TODO: Use config option, explain how it works */ + + /* Set aperture to 32 MB. */ + /* TODO: Use config option, explain how it works. */ pci_write_config32(dev, 0x94, 0x00010f38); - /* Set GART Table Base Address (31:12) */ + /* Set GART Table Base Address (31:12). */ pci_write_config32(dev, 0x98, (0x1558 << 12)); - /* Set AGP Aperture Base */ + /* Set AGP Aperture Base. */ pci_write_config32(dev, 0x10, 0xf8000008); - /* Enable CPU/PMSTR GART Access */ + /* Enable CPU/PMSTR GART Access. */ reg32 = pci_read_config8(dev, 0xbf); reg32 |= 0x80; pci_write_config8(dev, 0xbf, reg32); - + /* Enable AGP Aperture. */ reg32 = pci_read_config32(dev, 0x94); reg32 |= (3 << 7); @@ -84,16 +88,17 @@ static void agp_init(device_t dev) /* AGP Control */ pci_write_config8(dev, 0xbc, 0x21); pci_write_config8(dev, 0xbd, 0xd2); - - /* AGP Pad, driving strength, and delay control */ - /* All this should be constant, seeing as the - * VGA controller is onboard */ + + /* + * AGP Pad, driving strength, and delay control. All this should be + * constant, seeing as the VGA controller is onboard. + */ pci_write_config8(dev, 0x40, 0xc7); pci_write_config8(dev, 0x41, 0xdb); pci_write_config8(dev, 0x42, 0x10); pci_write_config8(dev, 0x43, 0xdb); pci_write_config8(dev, 0x44, 0x24); - + /* AGPC CKG Control */ pci_write_config8(dev, 0xc0, 0x02); pci_write_config8(dev, 0xc1, 0x02); @@ -108,27 +113,30 @@ static const struct device_operations agp_operations = { }; static const struct pci_driver agp_driver __pci_driver = { - .ops = &agp_operations, + .ops = &agp_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN700_AGP, }; -/* This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the -config in this device takes presidence. We configure both just to be safe. */ +/* + * This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the + * config in this device takes presidence. We configure both just to be safe. + */ static void agp_bridge_init(device_t dev) { - printk_debug("Setting up AGP Bridge device\n"); + printk_debug("Setting up AGP bridge device\n"); + pci_write_config16(dev, 0x4, 0x0007); /* Secondary Bus Number */ pci_write_config8(dev, 0x19, 0x01); /* Subordinate Bus Number */ pci_write_config8(dev, 0x1a, 0x01); - /* IO Base */ + /* I/O Base */ pci_write_config8(dev, 0x1c, 0xd0); - /* IO Limit */ + /* I/O Limit */ pci_write_config8(dev, 0x1d, 0xd0); - + /* Memory Base */ pci_write_config16(dev, 0x20, 0xfb00); /* Memory Limit */ @@ -159,7 +167,7 @@ static const struct device_operations agp_bridge_operations = { }; static const struct pci_driver agp_bridge_driver __pci_driver = { - .ops = &agp_bridge_operations, + .ops = &agp_bridge_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN700_BRIDGE, }; -- cgit v1.2.3