From ec558682fc11a985eb1b02b400a86ea9de407796 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Wed, 9 Jan 2019 13:33:39 +0200
Subject: aopen/dxplplusu: Move timestamps to common code
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First initialisation is already in cpu/intel/car/romstage.c.

Change-Id: If3e5068b4a9981354f0fca5fc12b6b81de1c8f4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/northbridge/intel/e7505/raminit.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/northbridge/intel')

diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 6550bb5cb6..70a0d66950 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -37,6 +37,7 @@
 #include <assert.h>
 #include <spd.h>
 #include <sdram_mode.h>
+#include <timestamp.h>
 
 #include "raminit.h"
 #include "e7505.h"
@@ -1768,6 +1769,8 @@ void e7505_mch_init(const struct mem_controller *memctrl)
 	RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
 	DUMPNORTH();
 
+	timestamp_add_now(TS_BEFORE_INITRAM);
+
 	sdram_set_registers(memctrl);
 	sdram_set_spd_registers(memctrl);
 	sdram_enable(memctrl);
@@ -1777,6 +1780,8 @@ void e7505_mch_done(const struct mem_controller *memctrl)
 {
 	sdram_post_ecc(memctrl);
 
+	timestamp_add_now(TS_AFTER_INITRAM);
+
 	RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
 	DUMPNORTH();
 }
-- 
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