From d4e5762bd72d4f8dae126bad695e111c381dddd4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 25 Dec 2017 17:01:33 +0100 Subject: nb/intel/x4x: Fix computing page_size This variable needs to be in byte so a division by 8 needs to happen. This problem was introduced by 3cf94032b "nb/x4x/raminit: Rewrite SPD decode and timing selection", but was probably not encountered because such dimms are rather uncommon. Change-Id: I2d57f5e584ac7fa1479791c239432005fe8c178d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/22991 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/northbridge/intel/x4x/raminit.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 37120dfe7c..013c2585ae 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -183,9 +183,10 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd, * 1KB page size. For the x16 configuration, the page size is 2KB * for all densities except the 256Mb device, which has a 1KB page * size." Micron, 'TN-47-16 Designing for High-Density DDR2 Memory' + * The formula is pagesize in KiB = width * 2^col_bits / 8. */ - s->dimms[dimm_idx].page_size = s->dimms[dimm_idx].width * - (1 << decoded_dimm.col_bits); + s->dimms[dimm_idx].page_size = decoded_dimm.width * + (1 << decoded_dimm.col_bits) / 8; switch (decoded_dimm.banks) { case 4: -- cgit v1.2.3