From cda9f93965c941719874764affc621b78ba145f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 18 Jul 2012 10:05:01 +0300 Subject: Intel SCH northbridge: fix resource index MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: If131ac9df89080faccd8ed952d6fc019483b5b2e Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/1237 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/intel/sch/northbridge.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 047d7dabc5..581f97c984 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -79,7 +79,7 @@ static void add_fixed_resources(struct device *dev, int index) u32 pcie_config_base, pcie_config_size; printk(BIOS_DEBUG, "Adding UMA memory area\n"); - resource = new_resource(dev, index); + resource = new_resource(dev, index++); resource->base = (resource_t) uma_memory_base; resource->size = (resource_t) uma_memory_size; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | @@ -87,7 +87,7 @@ static void add_fixed_resources(struct device *dev, int index) if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar\n"); - resource = new_resource(dev, index + 1); + resource = new_resource(dev, index++); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | @@ -95,7 +95,7 @@ static void add_fixed_resources(struct device *dev, int index) } printk(BIOS_DEBUG, "Adding CMC shadow area\n"); - resource = new_resource(dev, index + 1); + resource = new_resource(dev, index++); resource->base = (resource_t) CMC_SHADOW; resource->size = (resource_t) (64 * 1024); resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | -- cgit v1.2.3