From b600d41c3fead3e47ae41cc594bb1ae7f10e45e0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 16 Jan 2021 16:33:48 +0100 Subject: nb/intel/ironlake: Print MCH dev/revision IDs and CAPID Given the lack of documentation for this platform, having this info in coreboot logs (e.g. from board_status) can be pretty useful. Change-Id: I6a743c1efc1b6da71589460a69bfe4785e3e77a2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/49576 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Arthur Heymans --- src/northbridge/intel/ironlake/raminit.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index a49bd0875f..daa088651f 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1480,10 +1480,14 @@ static void collect_system_info(struct raminfo *info) info->memory_reserved_for_heci_mb = intel_early_me_uma_size(); } - for (i = 0; i < 3; i++) - gav(capid0[i] = - pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2))); - gav(info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID)); + for (i = 0; i < 3; i++) { + capid0[i] = pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2)); + printk(BIOS_DEBUG, "CAPID0[%d] = 0x%08x\n", i, capid0[i]); + } + info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID); + printk(BIOS_DEBUG, "Revision ID: 0x%x\n", info->revision); + printk(BIOS_DEBUG, "Device ID: 0x%x\n", pci_read_config16(NORTHBRIDGE, PCI_DEVICE_ID)); + info->max_supported_clock_speed_index = (~capid0[1] & 7); if ((capid0[1] >> 11) & 1) -- cgit v1.2.3