From a9068aa4e058a72b0cdeaffa423db17d7dd09fc6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 24 Nov 2018 09:31:10 +0100 Subject: nb/intel/i945/early_init.c: Correct the PEG_LC address of DEV(0:01.0) This bug/typo was spoted by Felix Held. As documented in the datasheet, to enable PMEGPE, HPGPE, GENGPE, we need to write 0x7 into DEV(0:01.0) register "PCI Express-G Legacy Control" located at 0xec. Used address at 0x114 to enable GPEs is likely a typo. Patch not tested. Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/27307 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/i945/early_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d516db76b9..39d660bf98 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -701,7 +701,7 @@ static void i945_setup_pci_express_x16(void) /* Enable GPEs */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec); reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xec, reg32); /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114); -- cgit v1.2.3