From a4ffe9dda0eb50eb698fef303f426408338fa0ff Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Mon, 27 Jun 2016 13:24:11 +0300
Subject: intel post-car: Separate files for setup_stack_and_mtrrs()
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Have a common romstage.c file to prepare CAR stack guards.

MTRR setup around cbmem_top() is somewhat northbridge specific,
place stubs under northbridge for platrform that will move
to RELOCATABLE_RAMSTAGE.

Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15762
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/northbridge/intel/gm45/ram_calc.c        | 6 ++++++
 src/northbridge/intel/i945/ram_calc.c        | 6 ++++++
 src/northbridge/intel/nehalem/ram_calc.c     | 6 ++++++
 src/northbridge/intel/sandybridge/ram_calc.c | 6 ++++++
 src/northbridge/intel/x4x/ram_calc.c         | 6 ++++++
 5 files changed, 30 insertions(+)

(limited to 'src/northbridge/intel')

diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 9a65e19c4c..92f1a7f7e3 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -21,6 +21,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
+#include <cpu/intel/romstage.h>
 #include <cbmem.h>
 #include "gm45.h"
 
@@ -105,3 +106,8 @@ void *cbmem_top(void)
 {
 	return (void *) smm_region_start();
 }
+
+void *setup_stack_and_mtrrs(void)
+{
+	return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 4349d19ea7..39ede5f75b 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -20,6 +20,7 @@
 #include <cbmem.h>
 #include "i945.h"
 #include <console/console.h>
+#include <cpu/intel/romstage.h>
 
 static uintptr_t smm_region_start(void)
 {
@@ -69,3 +70,8 @@ u32 decode_igd_memory_size(const u32 gms)
 
 	return ggc2uma[gms] << 10;
 }
+
+void *setup_stack_and_mtrrs(void)
+{
+	return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index 60ac2a7010..4d73ee9fc2 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -17,6 +17,7 @@
 
 #include <arch/io.h>
 #include <cbmem.h>
+#include <cpu/intel/romstage.h>
 #include "nehalem.h"
 
 static uintptr_t smm_region_start(void)
@@ -30,3 +31,8 @@ void *cbmem_top(void)
 {
 	return (void *) smm_region_start();
 }
+
+void *setup_stack_and_mtrrs(void)
+{
+	return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
index fff420a6c6..125f808fd1 100644
--- a/src/northbridge/intel/sandybridge/ram_calc.c
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -17,6 +17,7 @@
 
 #include <arch/io.h>
 #include <cbmem.h>
+#include <cpu/intel/romstage.h>
 #include "sandybridge.h"
 
 static uintptr_t smm_region_start(void)
@@ -30,3 +31,8 @@ void *cbmem_top(void)
 {
 	return (void *) smm_region_start();
 }
+
+void *setup_stack_and_mtrrs(void)
+{
+	return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 5a6a7675f1..09eec47e72 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -23,6 +23,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
+#include <cpu/intel/romstage.h>
 #include <northbridge/intel/x4x/x4x.h>
 
 /** Decodes used Graphics Mode Select (GMS) to kilobytes. */
@@ -93,3 +94,8 @@ void *cbmem_top(void)
 	u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG);
 	return (void*)(ramtop);
 }
+
+void *setup_stack_and_mtrrs(void)
+{
+	return (void*)CONFIG_RAMTOP;
+}
-- 
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