From a342f3937e7ce159fd170ab8cd26ba799a3bc9e4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 17 Oct 2018 10:56:26 +0200 Subject: src: Remove unneeded whitespace Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/intel/e7505/debug.c | 3 ++- src/northbridge/intel/fsp_rangeley/northbridge.c | 2 +- src/northbridge/intel/haswell/raminit.c | 2 +- src/northbridge/intel/nehalem/early_init.c | 2 +- src/northbridge/intel/nehalem/raminit.c | 2 +- src/northbridge/intel/pineview/early_init.c | 4 ++-- src/northbridge/intel/pineview/raminit.c | 14 +++++++------- src/northbridge/intel/sandybridge/raminit_ivy.c | 2 +- src/northbridge/intel/sandybridge/raminit_mrc.c | 2 +- src/northbridge/intel/x4x/dq_dqs.c | 2 +- 10 files changed, 18 insertions(+), 17 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index c085c874c9..f3a27e2b73 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -148,7 +148,8 @@ void dump_smbus_registers(void) printk(BIOS_DEBUG, "\n"); for (device = 1; device < 0x80; device++) { int j; - if ( spd_read_byte(device, 0) < 0 ) continue; + if (spd_read_byte(device, 0) < 0) + continue; printk(BIOS_DEBUG, "smbus: %02x", device); for (j = 0; j < 256; j++) { int status; diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 72b2761917..94855cfc40 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -131,7 +131,7 @@ static void mc_add_dram_resources(struct device *dev) mmio_resource(dev, index++, tomlow >> 10, (bmbound - bsmmrrl) >> 10); if (bmbound_hi > 0x100000000) { - ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10 ); + ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (bmbound_hi - 0x100000000) >> 20); } diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 21767b9416..221d71f1af 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -180,7 +180,7 @@ void sdram_initialize(struct pei_data *pei_data) */ u32 version = MCHBAR32(0x5034); printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", - version >> 24 , (version >> 16) & 0xff, + version >> 24, (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); report_memory_config(); diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 59c7741d48..ac0ed45d4c 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -36,7 +36,7 @@ static void nehalem_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 33f9c4869e..3160039092 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1420,7 +1420,7 @@ static void program_total_memory_map(struct raminfo *info) TOM = 4032; TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64); TOLUD = ALIGN_DOWN(min(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) - , TOUUD), 64); + , TOUUD), 64); memory_remap = 0; if (TOUUD - TOLUD > 64) { memory_remap = 1; diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 3984fb7a07..7f90529ef2 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -181,9 +181,9 @@ static void pineview_setup_bars(void) printk(BIOS_DEBUG, "Setting up static southbridge registers..."); pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */ + pci_write_config8(LPC, 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI */ pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(LPC, 0x4c /* GC */ , 0x10); /* Enable GPIOs */ + pci_write_config8(LPC, 0x4c /* GC */, 0x10); /* Enable GPIOs */ pci_write_config32(LPC, 0x88, 0x007c0291); pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 5adf865433..778b2f7f52 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -57,13 +57,13 @@ #define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) #define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0) -#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ +#define ONLY_DIMMA_IS_POPULATED(dimms, ch) (\ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) -#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ +#define ONLY_DIMMB_IS_POPULATED(dimms, ch) (\ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) -#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ +#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) (\ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) #define FOR_EACH_DIMM(idx) \ @@ -905,11 +905,11 @@ static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9); reg32 |= ((u32) pll->dbsel[f][clk]) << dqs; MCHBAR32(0x5b4+rank*4) = (MCHBAR32(0x5b4+rank*4) & - ~( (1 << (dqs+9))|(1 << dqs) )) | reg32; + ~((1 << (dqs+9))|(1 << dqs))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs*2) + 16); MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) & - ~( (1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)) )) | reg32; + ~((1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)))) | reg32; reg8 = pll->pi[f][clk]; MCHBAR8(0x520+j) = (MCHBAR8(0x520+j) & ~0x3f) | reg8; @@ -930,11 +930,11 @@ static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk) reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9); reg32 |= ((u32) pll->dbsel[f][clk]) << dq; MCHBAR32(0x5a4+rank*4) = (MCHBAR32(0x5a4+rank*4) & - ~( (1 << (dq+9))|(1 << dq) )) | reg32; + ~((1 << (dq+9))|(1 << dq))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) & - ~( (1 << (dq*2 + 1))|(1 << (dq*2)) )) | reg32; + ~((1 << (dq*2 + 1))|(1 << (dq*2)))) | reg32; reg8 = pll->pi[f][clk]; MCHBAR8(0x500+j) = (MCHBAR8(0x500+j) & ~0x3f) | reg8; diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 88d8bd6348..20f30389d8 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -225,7 +225,7 @@ static u8 get_XP(u32 tCK, u8 base_freq) * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | * XP : | 3 | 4 | 4 | 5 | 6 | 7 | 8 | 8 | */ - static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 , 8, 8 }; + static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7, 8, 8 }; xp = frq_xp_map[get_FRQ(tCK, 133) - 3]; } diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 0c3751f57e..1975051207 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -248,7 +248,7 @@ void sdram_initialize(struct pei_data *pei_data) */ u32 version = MCHBAR32(0x5034); printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", - version >> 24 , (version >> 16) & 0xff, + version >> 24, (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); /* Send ME init done for SandyBridge here. This is done diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index fbdb4f9f17..d5526f6a22 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -463,7 +463,7 @@ int do_read_training(struct sysinfo *s) struct rt_dqs_setting dqs_setting[TOTAL_BYTELANES]; u16 saved_dqs_center[TOTAL_CHANNELS][TOTAL_BYTELANES]; - memset(saved_dqs_center, 0 , sizeof(saved_dqs_center)); + memset(saved_dqs_center, 0, sizeof(saved_dqs_center)); printk(BIOS_DEBUG, "Starting DQS read training\n"); -- cgit v1.2.3