From 9fe50695841aa44713f5ee0486ca25f7d39b724e Mon Sep 17 00:00:00 2001 From: Jonathan Kollasch Date: Tue, 19 Oct 2010 13:39:38 +0000 Subject: Correct spelling of "spacing" (in comments). Signed-off-by: Jonathan Kollasch Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/intel/i855/raminit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 604a5e1f59..539d161640 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -755,7 +755,7 @@ static void spd_set_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_ */ /* - * Back to Back Read-Write command spaceing (DDR, different Rows/Bank) + * Back to Back Read-Write command spacing (DDR, different Rows/Bank) */ /* Set to a 3 clock back to back read to write turn around. * 2 is a good delay if the CAS latency is 2.0 */ @@ -766,7 +766,7 @@ static void spd_set_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_ dram_timing |= (1 << 28); // 3 clocks /* - * Back to Back Read-Write command spaceing (DDR, same or different Rows/Bank) + * Back to Back Read-Write command spacing (DDR, same or different Rows/Bank) */ dram_timing &= ~(3 << 26); if (current_cas_latency == DRT_CAS_2_0) -- cgit v1.2.3