From 92f46aaac7104c62ab3956dc32af5ccbddc944f1 Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Tue, 15 Sep 2020 08:42:17 +0200
Subject: src: Include <arch/io.h> when appropriate

Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/i945/early_init.c   | 1 -
 src/northbridge/intel/ironlake/romstage.c | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/northbridge/intel')

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index b04a2f5940..dea4f9b72b 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/io.h>
 #include <cbmem.h>
 #include <cf9_reset.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c
index e5ecafe2a2..6b9f3d0e83 100644
--- a/src/northbridge/intel/ironlake/romstage.c
+++ b/src/northbridge/intel/ironlake/romstage.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <arch/io.h>
 #include <stdint.h>
 #include <console/console.h>
 #include <cf9_reset.h>
-- 
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