From 9137cbd5e4bc7040282ce9eb6fb75e8f251bcffa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 29 Sep 2019 07:03:37 +0300 Subject: intel/i945: Delay bridge VGA IO enable to ramstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35676 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/i945/early_init.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 791baecc6a..c53577b40d 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -661,11 +661,6 @@ static void i945_setup_pci_express_x16(void) reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); - - /* Set VGA enable bit in PCIe bridge */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_VGA; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); } /* Enable GPEs */ -- cgit v1.2.3