From 75d139bdf28077c46b144f8380bb275fddb1bb6b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 17 Jun 2016 10:00:28 +0300 Subject: intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib3250677ee926deaa957c83aca7479eb0159358c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15231 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/intel/sandybridge/romstage.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index df0c5bbba5..a2ca1c1835 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -43,7 +43,10 @@ static void early_pch_init(void) pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); } -void main(unsigned long bist) +/* Platform has no romstage entry point under mainboard directory, + * so this one is named with prefix mainboard. + */ +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; -- cgit v1.2.3