From 6a2a5142d5d18e44a4ec0268e51d594fa0e7a147 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 14 Jun 2021 09:39:01 +0200 Subject: nb/intel/haswell: Fully handle GDXCBAR and EDRAMBAR GDXCBAR and EDRAMBAR are accounted for when reporting resources to the allocator, but they are not present in the DSDT. In addition, coreboot does not enable either range, but MRC.bin sets up GDXCBAR and does not disable it afterwards. Not reporting GDXCBAR in the DSDT can result in resource conflicts, and not enabling EDRAMBAR can cause issues on CPUs with eDRAM. Enable both GDXCBAR and EDRAMBAR in coreboot code, and report these ranges in the DSDT. This matches what Broadwell does. The value for the `GDXC_BASE_ADDRESS` macro matches what MRC.bin programs as well. Tested on Asrock B85M Pro4 with an i7-4770S (no eDRAM): - Still boots - EDRAMBAR is now enabled with base address of 0xfed80000 - GDXCBAR is still mapped with base address of 0xfed84000 Change-Id: I5538873b30e3d02053e4ba125528d32453ef6572 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/55480 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/haswell/acpi/hostbridge.asl | 2 ++ src/northbridge/intel/haswell/early_init.c | 3 +++ src/northbridge/intel/haswell/memmap.h | 2 ++ 3 files changed, 7 insertions(+) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 5c22ce1664..0aa76a5add 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -182,6 +182,8 @@ Device (PDRC) Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH + Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE) + Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE) }) // Current Resource Settings diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 15a0b1b043..13c2dcd2bc 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -21,6 +21,9 @@ static void haswell_setup_bars(void) pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); pci_write_config32(HOST_BRIDGE, DMIBAR + 4, 0); + mchbar_write32(EDRAMBAR, EDRAM_BASE_ADDRESS | 1); + mchbar_write32(GDXCBAR, GDXC_BASE_ADDRESS | 1); + /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(HOST_BRIDGE, PAM0, 0x30); pci_write_config8(HOST_BRIDGE, PAM1, 0x33); diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h index 92beeece49..fd2317fc68 100644 --- a/src/northbridge/intel/haswell/memmap.h +++ b/src/northbridge/intel/haswell/memmap.h @@ -9,8 +9,10 @@ #define EP_BASE_SIZE 0x1000 +#define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 +#define GDXC_BASE_ADDRESS 0xfed84000 #define GDXC_BASE_SIZE 0x1000 #define GFXVT_BASE_ADDRESS 0xfed90000ULL -- cgit v1.2.3