From 6724ba4f045cbbe2326463cbeaf59becfb01342e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 31 Jan 2021 15:06:59 +0100 Subject: memory_info.h: Store SMBIOS error correction type There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178 Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/raminit.c | 6 +++--- src/northbridge/intel/sandybridge/raminit.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 96e6a2aeff..58ac8a05a3 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -167,9 +167,9 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } -static bool nb_supports_ecc(const uint32_t capid0_a) +static uint8_t nb_get_ecc_type(const uint32_t capid0_a) { - return !(capid0_a & CAPID_ECCDIS); + return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; } static uint16_t nb_slots_per_channel(const uint32_t capid0_a) @@ -256,7 +256,7 @@ void setup_sdram_meminfo(struct pei_data *pei_data) const uint16_t channels = nb_number_of_channels(capid0_a); - mem_info->ecc_capable = nb_supports_ecc(capid0_a); + mem_info->ecc_type = nb_get_ecc_type(capid0_a); mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a); } diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0dcd952595..47cd7dee50 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -53,9 +53,9 @@ static void disable_channel(ramctr_timing *ctrl, int channel) memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); } -static bool nb_supports_ecc(const uint32_t capid0_a) +static uint8_t nb_get_ecc_type(const uint32_t capid0_a) { - return !(capid0_a & CAPID_ECCDIS); + return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; } static uint16_t nb_slots_per_channel(const uint32_t capid0_a) @@ -114,7 +114,7 @@ static void setup_sdram_meminfo(ramctr_timing *ctrl) const uint16_t channels = nb_number_of_channels(capid0_a); - m->ecc_capable = nb_supports_ecc(capid0_a); + m->ecc_type = nb_get_ecc_type(capid0_a); m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); m->number_of_devices = channels * nb_slots_per_channel(capid0_a); } -- cgit v1.2.3