From 6473473417bfb0ce4961cbce8b80c29786e1d39f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 18 Jan 2021 00:30:23 +0100 Subject: nb/intel/ironlake/northbridge.c: Improve readability This cosmetic change does 2 things: - change bitwise shifting to division - Make the division by / KiB explicit for fixed legacy ranges like 0xa0000-0xbffff. Change-Id: If4e05f496abc05e06a944b244824376f3937a57b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/49621 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons --- src/northbridge/intel/ironlake/northbridge.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index a1d03efe7f..e01bf7dae1 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -9,6 +9,7 @@ #include #include #include "chip.h" +#include #include "ironlake.h" #include @@ -52,10 +53,8 @@ static void add_fixed_resources(struct device *dev, int index) resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); - - reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); - + mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k); + reserved_ram_resource(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB); } #if CONFIG(HAVE_ACPI_TABLES) @@ -105,10 +104,10 @@ static void mc_read_resources(struct device *dev) printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud); /* Report the memory regions */ - ram_resource(dev, index++, 0, 640); - ram_resource(dev, index++, 768, ((tseg_base >> 10) - 768)); + ram_resource(dev, index++, 0, 0xa0000 / KiB); + ram_resource(dev, index++, 0xc0000 / KiB, (tseg_base - 0xc0000) / KiB); - mmio_resource(dev, index++, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); + mmio_resource(dev, index++, tseg_base / KiB, CONFIG_SMM_TSEG_SIZE / KiB); reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); const int uma_sizes_gtt[16] = @@ -130,17 +129,17 @@ static void mc_read_resources(struct device *dev) if (gtt_base > tseg_end) { /* Reserve the gap. MMIO doesn't work in this range. Keep it uncacheable, though, for easier MTRR allocation. */ - mmio_resource(dev, index++, tseg_end >> 10, (gtt_base - tseg_end) >> 10); + mmio_resource(dev, index++, tseg_end / KiB, (gtt_base - tseg_end) / KiB); } - mmio_resource(dev, index++, gtt_base >> 10, uma_size_gtt << 10); - mmio_resource(dev, index++, igd_base >> 10, uma_size_igd << 10); + mmio_resource(dev, index++, gtt_base / KiB, uma_size_gtt * KiB); + mmio_resource(dev, index++, igd_base / KiB, uma_size_igd * KiB); if (touud > 4096) - ram_resource(dev, index++, (4096 << 10), ((touud - 4096) << 10)); + ram_resource(dev, index++, (4096 * KiB), ((touud - 4096) * KiB)); /* This memory is not DMA-capable. */ if (touud >= 8192 - 64) - bad_ram_resource(dev, index++, 0x1fc000000ULL >> 10, 0x004000000 >> 10); + bad_ram_resource(dev, index++, 0x1fc000000ULL / KiB, 0x004000000 / KiB); add_fixed_resources(dev, index); } -- cgit v1.2.3