From 6372a0eef14dd97f2743d7d1820e2446cc997bd2 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 30 Oct 2016 18:39:53 +0100 Subject: nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)" Change-Id: I230b5425ac9e916a5ee10a49eeaf5d6d44fd49e6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/17192 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- src/northbridge/intel/i945/early_init.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 4373167693..5d1a0c28c3 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -90,9 +90,9 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC - printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); -#endif + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) + printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } static void i945_detect_chipset(void) @@ -139,9 +139,9 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM - printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); -#endif + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } static void i945_setup_bars(void) -- cgit v1.2.3