From 55409ebbb65cd52c4f5c47f0c1232e8bef0cc4a3 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 15 Jun 2016 20:28:32 +0200 Subject: nb/intel/sandybridge/raminit: Use supported CAS Instead of programming unsupported CAS use the highest supported value. Start at DDR3 maximum of CAS 18T. Increase error message verbosity level. Useful for overclocking. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Allows to run a DDR3-1600 DIMM at 933Mhz. Change-Id: I2e8aadd541f06fa032ad7095c9a2d5e3bb7613f3 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/15217 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Alexander Couzens --- src/northbridge/intel/sandybridge/raminit.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index ba03bbbc92..cf66a0d54c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -722,8 +722,16 @@ static void dram_timing(ramctr_timing * ctrl) val++; } /* Is CAS supported */ - if (!(ctrl->cas_supported & (1 << (val - 4)))) - printk(BIOS_DEBUG, "CAS not supported\n"); + if (!(ctrl->cas_supported & (1 << (val - 4)))) { + printk(BIOS_ERR, "CAS %uT not supported. ", val); + val = 18; + /* Find highest supported CAS latency */ + while (!((ctrl->cas_supported >> (val - 4)) & 1)) + val--; + + printk(BIOS_ERR, "Using CAS %uT instead.\n", val); + } + printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); ctrl->CAS = val; ctrl->CWL = get_CWL(ctrl->CAS); -- cgit v1.2.3