From 546953c0c553465761705fb0747964c08d634461 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 29 Nov 2014 10:38:17 +0100 Subject: Replace hlt with halt() There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Paul Menzel --- src/northbridge/intel/gm45/early_reset.c | 3 ++- src/northbridge/intel/i5000/raminit.c | 5 +++-- src/northbridge/intel/i945/early_init.c | 3 ++- src/northbridge/intel/i945/raminit.c | 5 +++-- src/northbridge/intel/nehalem/raminit.c | 20 ++++++-------------- src/northbridge/intel/sandybridge/raminit.c | 4 ++-- 6 files changed, 18 insertions(+), 22 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index fccb97f612..babb99478d 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -21,6 +21,7 @@ #include #include +#include #include "gm45.h" void gm45_early_reset(void/*const timings_t *const timings*/) @@ -69,5 +70,5 @@ void gm45_early_reset(void/*const timings_t *const timings*/) /* Perform system reset through CF9 interface. */ outb(0x02, 0xcf9); /* Set system reset bit. */ outb(0x06, 0xcf9); /* Set cpu reset bit, too. */ - while (1) asm("hlt"); + halt(); } diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 9c694c7d28..539400293b 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -1522,7 +1523,7 @@ static void i5000_try_restart(const char *msg) printk(BIOS_INFO, "%s", msg); i5000_dump_error_registers(); outb(0x06, 0xcf9); - for(;;) asm volatile("hlt"); + halt(); } static void i5000_pam_setup(void) @@ -1624,7 +1625,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup) pci_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq); /* FSB:FBD mapping changed, needs hard reset */ outb(0x06, 0xcf9); - for(;;) asm volatile("hlt"); + halt(); } return 0; } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index f639aef146..aaa17e503b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "i945.h" @@ -512,7 +513,7 @@ static void i945_setup_dmi_rcrb(void) reg32 |= (3 << 0); DMIBAR32(0x224) = reg32; outb(0x06, 0xcf9); - for (;;) asm("hlt"); /* wait for reset */ + halt(); /* wait for reset */ } } } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e823bab455..e9b6e3ffed 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include "raminit.h" #include "i945.h" @@ -281,7 +282,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Reset required.\n"); outb(0x00, 0xcf9); outb(0x0e, 0xcf9); - for (;;) asm("hlt"); /* Wait for reset! */ + halt(); /* Wait for reset! */ } } @@ -311,7 +312,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Reset required.\n"); outb(0x00, 0xcf9); outb(0x0e, 0xcf9); - for (;;) asm("hlt"); /* Wait for reset! */ + halt(); /* Wait for reset! */ } } diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 74ddb4b3ff..fb82484444 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -38,6 +37,7 @@ #include #include #include +#include #include #include "raminit.h" #include @@ -3805,9 +3805,7 @@ void chipset_init(const int s3resume) write_mchbar8(0x2ca8, 0); outb(0x6, 0xcf9); #if REAL - while (1) { - asm volatile ("hlt"); - } + halt(); #else printf("CP5\n"); exit(0); @@ -4041,9 +4039,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) "Interrupted RAM init, reset required.\n"); outb(0x6, 0xcf9); #if REAL - while (1) { - asm volatile ("hlt"); - } + halt(); #endif } } @@ -4407,9 +4403,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) + 4); write_mchbar32(0x1af0, read_mchbar32(0x1af0) | 0x10); #if REAL - while (1) { - asm volatile ("hlt"); - } + halt(); #else printf("CP5\n"); exit(0); @@ -4510,9 +4504,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) outb(0xe, 0xcf9); #if REAL - while (1) { - asm volatile ("hlt"); - } + halt(); #else printf("CP5\n"); exit(0); @@ -4990,7 +4982,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) /* Failed S3 resume, reset to come up cleanly */ outb(0xe, 0xcf9); - hlt(); + halt(); } #endif } diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index d2ae4b039e..f6c92dbd11 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -29,6 +28,7 @@ #include #include #include +#include #include "raminit.h" #include "pei_data.h" #include "sandybridge.h" @@ -239,7 +239,7 @@ void sdram_initialize(struct pei_data *pei_data) if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Pass console handler in pei_data */ -- cgit v1.2.3