From 3b452e0a797b54a05b97725f4e4e320c51098754 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 3 Oct 2019 09:16:10 +0200 Subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC generic IO decode up in romstage based on devicetree settings - Remove the ramstage LPC generic IO decode from ramstage as this is now done in romstage.c - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock. Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35772 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/nehalem/romstage.c | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c index 83848273a0..c465a99365 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/nehalem/romstage.c @@ -30,8 +30,6 @@ #include #include #include -#include -#include /* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. @@ -47,29 +45,7 @@ void mainboard_romstage_entry(void) /* TODO, make this configurable */ nehalem_early_initialization(NEHALEM_MOBILE); - /* mainboard_lpc_init */ - mainboard_lpc_init(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* TODO, make this configurable */ - pch_setup_cir(NEHALEM_MOBILE); - - southbridge_configure_default_intmap(); - - /* Must set BIT0 (hides performance counters PCI device). - coreboot enables the Rate Matching Hub which makes the UHCI PCI - devices disappear, so BIT5-12 and BIT28 can be set to hide those. */ - RCBA32(FD) = (1 << 28) | (0xff << 5) | 1; - - /* Set reserved bit to 1 */ - RCBA32(FD2) = 1; - - early_usb_init(mainboard_usb_ports); + early_pch_init(); /* Initialize console device(s) */ console_init(); -- cgit v1.2.3