From 360d94745feea766de7ef19487ba9158221faca0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 18:11:03 +0100 Subject: nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCK There is some overlap between romstage and bootblock. LPC setup and BAR initialization is now done twice. The rationale is that the romstage should not depend too much on the bootblock, since it can reside in a RO fmap region. Enabling the console will be done in a followup patch. Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/sandybridge/Kconfig | 4 ---- src/northbridge/intel/sandybridge/Makefile.inc | 3 ++- src/northbridge/intel/sandybridge/bootblock.c | 7 +++---- 3 files changed, 5 insertions(+), 9 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 288dd093bf..0502b50014 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -62,10 +62,6 @@ config VGA_BIOS_ID string default "8086,0106" -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/sandybridge/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xf0000000 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 77d1fdbb84..7390d2b40b 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y) +bootblock-y += bootblock.c + ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += pcie.c @@ -44,7 +46,6 @@ mrc.bin-type := mrc endif romstage-y += romstage.c romstage-y += early_init.c -romstage-y += ../../../arch/x86/walkcbfs.S smm-y += finalize.c diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 15e2de1bcc..40819bf7eb 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -12,11 +12,10 @@ */ #include +#include +#include "sandybridge.h" -/* Just re-define this instead of including sandybridge.h. It blows up romcc. */ -#define PCIEXBAR 0x60 - -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; -- cgit v1.2.3