From 2ed0aa258f4bcbf978998ccd3a76f7b1c2d3d031 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Tue, 5 Jan 2016 20:58:58 -0700 Subject: Correct some common spelling mistakes - occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- src/northbridge/intel/i945/raminit.c | 58 ++++++++++++++++++------------------ src/northbridge/intel/x4x/raminit.c | 2 +- 2 files changed, 30 insertions(+), 30 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b1bd2ec44b..59a31deacf 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2167,8 +2167,8 @@ static void sdram_program_clock_crossing(void) #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ 0x08040120, 0x00000000, /* DDR400 FSB533 */ 0x00100401, 0x00000000, /* DDR533 FSB533 */ @@ -2178,51 +2178,51 @@ static void sdram_program_clock_crossing(void) 0x10040280, 0x00000040, /* DDR533 FSB667 */ 0x00100401, 0x00000000, /* DDR667 FSB667 */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ }; static const u32 command_clock_crossing[] = { 0x04020208, 0x00000000, /* DDR400 FSB400 */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ 0x00060108, 0x00000000, /* DDR400 FSB533 */ 0x04020108, 0x00000000, /* DDR533 FSB533 */ - 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistent */ 0x00040318, 0x00000000, /* DDR400 FSB667 */ 0x04020118, 0x00000000, /* DDR533 FSB667 */ 0x02010804, 0x00000000, /* DDR667 FSB667 */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ }; #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC /* i945 G/P */ static const u32 data_clock_crossing[] = { - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ 0x10080201, 0x00000000, /* DDR400 FSB533 */ 0x00100401, 0x00000000, /* DDR533 FSB533 */ 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ 0x04020108, 0x00000000, /* DDR400 FSB800 */ 0x00020108, 0x00000000, /* DDR533 FSB800 */ @@ -2234,17 +2234,17 @@ static void sdram_program_clock_crossing(void) }; static const u32 command_clock_crossing[] = { - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ 0x00010800, 0x00000402, /* DDR400 FSB533 */ 0x01000400, 0x00000200, /* DDR533 FSB533 */ 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ - 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ + 0xffffffff, 0xffffffff, /* nonexistent */ 0x02010804, 0x00000000, /* DDR400 FSB800 */ 0x00010402, 0x00000000, /* DDR533 FSB800 */ diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 613011fa98..f5a4e5ff51 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -38,7 +38,7 @@ static void sdram_read_spds(struct sysinfo *s) int status = 0; FOR_EACH_DIMM(i) { if (s->spd_map[i] == 0) { - /* Non-existant SPD address */ + /* Non-existent SPD address */ s->dimms[i].card_type = 0; continue; } -- cgit v1.2.3