From 264566c177dac98e67c2a4765fe08c5d8de10753 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 15 Oct 2017 15:06:48 -0600 Subject: Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/northbridge/intel/i3100/Kconfig | 11 - src/northbridge/intel/i3100/Makefile.inc | 7 - src/northbridge/intel/i3100/chip.h | 25 - src/northbridge/intel/i3100/ep80579.h | 59 - src/northbridge/intel/i3100/i3100.h | 68 -- src/northbridge/intel/i3100/memory_initialized.c | 24 - src/northbridge/intel/i3100/northbridge.c | 220 ---- src/northbridge/intel/i3100/pciexp_porta.c | 85 -- src/northbridge/intel/i3100/pciexp_porta_ep80579.c | 107 -- src/northbridge/intel/i3100/raminit.c | 1201 -------------------- src/northbridge/intel/i3100/raminit.h | 31 - src/northbridge/intel/i3100/raminit_ep80579.c | 693 ----------- src/northbridge/intel/i3100/raminit_ep80579.h | 27 - src/northbridge/intel/i3100/reset_test.c | 20 - 14 files changed, 2578 deletions(-) delete mode 100644 src/northbridge/intel/i3100/Kconfig delete mode 100644 src/northbridge/intel/i3100/Makefile.inc delete mode 100644 src/northbridge/intel/i3100/chip.h delete mode 100644 src/northbridge/intel/i3100/ep80579.h delete mode 100644 src/northbridge/intel/i3100/i3100.h delete mode 100644 src/northbridge/intel/i3100/memory_initialized.c delete mode 100644 src/northbridge/intel/i3100/northbridge.c delete mode 100644 src/northbridge/intel/i3100/pciexp_porta.c delete mode 100644 src/northbridge/intel/i3100/pciexp_porta_ep80579.c delete mode 100644 src/northbridge/intel/i3100/raminit.c delete mode 100644 src/northbridge/intel/i3100/raminit.h delete mode 100644 src/northbridge/intel/i3100/raminit_ep80579.c delete mode 100644 src/northbridge/intel/i3100/raminit_ep80579.h delete mode 100644 src/northbridge/intel/i3100/reset_test.c (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig deleted file mode 100644 index a7c4a1daab..0000000000 --- a/src/northbridge/intel/i3100/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -config NORTHBRIDGE_INTEL_I3100 - bool - select NO_MMCONF_SUPPORT - select LATE_CBMEM_INIT - -if NORTHBRIDGE_INTEL_I3100 -config DIMM_MAP_LOGICAL - hex - default 0x1248 - -endif diff --git a/src/northbridge/intel/i3100/Makefile.inc b/src/northbridge/intel/i3100/Makefile.inc deleted file mode 100644 index 16291bf5d8..0000000000 --- a/src/northbridge/intel/i3100/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I3100),y) - -ramstage-y += northbridge.c -ramstage-y += pciexp_porta.c -ramstage-y += pciexp_porta_ep80579.c - -endif diff --git a/src/northbridge/intel/i3100/chip.h b/src/northbridge/intel/i3100/chip.h deleted file mode 100644 index 5da74318ce..0000000000 --- a/src/northbridge/intel/i3100/chip.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_I3100_CHIP_H -#define NORTHBRIDGE_INTEL_I3100_CHIP_H - -struct northbridge_intel_i3100_config -{ - /* Interrupt line connect */ - u16 intrline; -}; - -#endif /* NORTHBRIDGE_INTEL_I3100_CHIP_H */ diff --git a/src/northbridge/intel/i3100/ep80579.h b/src/northbridge/intel/i3100/ep80579.h deleted file mode 100644 index 60c319f593..0000000000 --- a/src/northbridge/intel/i3100/ep80579.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_I3100_EP80579_H -#define NORTHBRIDGE_INTEL_I3100_EP80579_H - -#define SMRBASE 0x14 -#define MCHCFG0 0x50 -#define FDHC 0x58 -#define PAM 0x59 -#define DRB 0x60 -#define DRT1 0x64 -#define DRA 0x70 -#define DRT0 0x78 -#define DRC 0x7c -#define ECCDIAG 0x84 -#define SDRC 0x88 -#define CKDIS 0x8c -#define CKEDIS 0x8d -#define DEVPRES 0x9c -#define DEVPRES_D0F0 (1 << 0) -#define DEVPRES_D1F0 (1 << 1) -#define DEVPRES_D2F0 (1 << 2) -#define DEVPRES_D3F0 (1 << 3) -#define DEVPRES_D4F0 (1 << 4) -#define DEVPRES_D10F0 (1 << 5) -#define EXSMRC 0x9d -#define SMRAM 0x9e -#define EXSMRAMC 0x9f -#define DDR2ODTC 0xb0 -#define TOLM 0xc4 -#define REMAPBASE 0xc6 -#define REMAPLIMIT 0xc8 -#define REMAPOFFSET 0xca -#define TOM 0xcc -#define HECBASE 0xce -#define DEVPRES1 0xf4 - -#define DCALCSR 0x040 -#define DCALADDR 0x044 -#define DCALDATA 0x048 -#define MBCSR 0x140 -#define MBADDR 0x144 -#define MBDATA 0x148 -#define DDRIOMC2 0x268 - -#endif diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h deleted file mode 100644 index b501e0b88a..0000000000 --- a/src/northbridge/intel/i3100/i3100.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __I3100_H__ -#define __I3100_H__ - -#define IURBASE 0X14 -#define MCHCFG0 0X50 -#define MCHSCRB 0X52 -#define FDHC 0X58 -#define PAM 0X59 -#define DRB 0X60 -#define DRA 0X70 -#define DRT 0X78 -#define DRC 0X7C -#define DRM 0X80 -#define DRORC 0X82 -#define ECCDIAG 0X84 -#define SDRC 0X88 -#define CKDIS 0X8C -#define CKEDIS 0X8D -#define DDRCSR 0X9A -#define DEVPRES 0X9C -#define DEVPRES_D0F0 (1 << 0) -#define DEVPRES_D1F0 (1 << 1) -#define DEVPRES_D2F0 (1 << 2) -#define DEVPRES_D3F0 (1 << 3) -#define DEVPRES_D4F0 (1 << 4) -#define DEVPRES_D5F0 (1 << 5) -#define DEVPRES_D6F0 (1 << 6) -#define DEVPRES_D7F0 (1 << 7) -#define ESMRC 0X9D -#define SMRC 0X9E -#define EXSMRC 0X9F -#define DDR2ODTC 0XB0 -#define TOLM 0XC4 -#define REMAPBASE 0XC6 -#define REMAPLIMIT 0XC8 -#define REMAPOFFSET 0XCA -#define TOM 0XCC -#define EXPECBASE 0XCE -#define DEVPRES1 0XF4 -#define DEVPRES1_D0F1 (1 << 5) -#define DEVPRES1_D8F0 (1 << 1) -#define MSCFG 0XF6 - -/* DRC */ -#define DRC_NOECC_MODE (0 << 20) -#define DRC_72BIT_ECC (1 << 20) - -#define RCBA 0xF0 -#define DEFAULT_RCBA ((u8 *)0xFEA00000) - -int bios_reset_detected(void); - -#endif diff --git a/src/northbridge/intel/i3100/memory_initialized.c b/src/northbridge/intel/i3100/memory_initialized.c deleted file mode 100644 index 6af7b9bca8..0000000000 --- a/src/northbridge/intel/i3100/memory_initialized.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "i3100.h" -#define NB_DEV PCI_DEV(0, 0, 0) - -static inline int memory_initialized(void) -{ - u32 drc; - drc = pci_read_config32(NB_DEV, DRC); - return (drc & (1<<29)); -} diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c deleted file mode 100644 index f05eea0464..0000000000 --- a/src/northbridge/intel/i3100/northbridge.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/northbridge/intel/e7520/northbridge.c */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include "i3100.h" -#include - - -static void pci_domain_set_resources(device_t dev) -{ - device_t mc_dev; - u32 pci_tolm; - - pci_tolm = find_pci_tolm(dev->link_list); - -#if 1 - printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); -#endif - /* FIXME Me temporary hack */ - if (pci_tolm > 0xe0000000) - pci_tolm = 0xe0000000; - /* Ensure pci_tolm is 128M aligned */ - pci_tolm &= 0xf8000000; - mc_dev = dev->link_list->children; - if (mc_dev) { - /* Figure out which areas are/should be occupied by RAM. - * This is all computed in kilobytes and converted to/from - * the memory controller right at the edges. - * Having different variables in different units is - * too confusing to get right. Kilobytes are good up to - * 4 Terabytes of RAM... - */ - u16 tolm_r, remapbase_r, remaplimit_r, remapoffset_r; - u32 tomk, tolmk; - u32 remapbasek, remaplimitk, remapoffsetk; - - /* Get the Top of Memory address, units are 128M */ - tomk = ((u32)pci_read_config16(mc_dev, TOM)) << 17; - /* Compute the Top of Low Memory */ - tolmk = (pci_tolm & 0xf8000000) >> 10; - - if (tolmk >= tomk) { - /* The PCI hole does not overlap memory - * we won't use the remap window. - */ - tolmk = tomk; - remapbasek = 0x3ff << 16; - remaplimitk = 0 << 16; - remapoffsetk = 0 << 16; - } - else { - /* The PCI memory hole overlaps memory - * setup the remap window. - */ - /* Find the bottom of the remap window - * is it above 4G? - */ - remapbasek = 4*1024*1024; - if (tomk > remapbasek) { - remapbasek = tomk; - } - /* Find the limit of the remap window */ - remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16)); - /* Find the offset of the remap window from tolm */ - remapoffsetk = remapbasek - tolmk; - } - /* Write the RAM configuration registers, - * preserving the reserved bits. - */ - tolm_r = pci_read_config16(mc_dev, 0xc4); - tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff); - pci_write_config16(mc_dev, 0xc4, tolm_r); - - remapbase_r = pci_read_config16(mc_dev, 0xc6); - remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00); - pci_write_config16(mc_dev, 0xc6, remapbase_r); - - remaplimit_r = pci_read_config16(mc_dev, 0xc8); - remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00); - pci_write_config16(mc_dev, 0xc8, remaplimit_r); - - remapoffset_r = pci_read_config16(mc_dev, 0xca); - remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00); - pci_write_config16(mc_dev, 0xca, remapoffset_r); - - /* Report the memory regions */ - ram_resource(dev, 3, 0, 640); - ram_resource(dev, 4, 768, (tolmk - 768)); - if (tomk > 4*1024*1024) { - ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024); - } - if (remaplimitk >= remapbasek) { - ram_resource(dev, 6, remapbasek, - (remaplimitk + 64*1024) - remapbasek); - } - - set_late_cbmem_top(tolmk * 1024); - } - assign_resources(dev->link_list); -} - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, -}; - -static void mc_read_resources(device_t dev) -{ - pci_dev_read_resources(dev); - - mmconf_resource(dev, EXPECBASE); -} - -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - u64 mmcfg; - - dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_MC, 0); // 0:0x13.0 - if (!dev) - return current; - - // MMCFG not supported or not enabled. - mmcfg = ((u64) pci_read_config16(dev, 0xce)) << 16; - if (!mmcfg) - return current; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - mmcfg, 0x0, 0x0, 0xff); - - return current; -} - -#endif - -static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, -}; - -static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, -}; - -static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_MC, -}; - -static void cpu_bus_init(device_t dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, -}; - - -static void enable_dev(device_t dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_intel_i3100_ops = { - CHIP_NAME("Intel 3100 Northbridge") - .enable_dev = enable_dev, -}; diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c deleted file mode 100644 index 3f4939cace..0000000000 --- a/src/northbridge/intel/i3100/pciexp_porta.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */ - -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include - -typedef struct northbridge_intel_i3100_config config_t; - -static void pcie_init(struct device *dev) -{ - config_t *config; - - /* Get the chip configuration */ - config = dev->chip_info; - - if (config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } - -} - -static void pcie_scan_bridge(struct device *dev) -{ - u16 val; - u16 ctl; - int flag = 0; - do { - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); - if ((val & (1<<10)) && (!flag)) { /* training error */ - ctl = pci_read_config16(dev, 0x74); - pci_write_config16(dev, 0x74, (ctl | (1<<5))); - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); - flag = 1; - hard_reset(); - } - } while (val & (3<<10)); - - pciexp_scan_bridge(dev); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver_0 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA0, -}; - -static const struct pci_driver pci_driver_1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA1, -}; diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c deleted file mode 100644 index 62f485d705..0000000000 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 4DSP Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/northbridge/intel/i3100/pciexp_porta.c */ - -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include - -typedef struct northbridge_intel_i3100_config config_t; - -static void pcie_init(struct device *dev) -{ - config_t *config; - u16 val; - - /* Get the chip configuration */ - config = dev->chip_info; - - if (config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } - - printk(BIOS_SPEW, "configure PCIe port as \"Slot Implemented\"\n"); - val = pci_read_config16(dev, 0x66); - val &= ~(1<<8); - val |= 1<<8; - pci_write_config16(dev, 0x66, val); - - /* Todo configure the PCIe bootstrap mode (covered by Intel NDA) */ -} - - -static void pcie_bus_enable_resources(struct device *dev) -{ - if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n"); - pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8); - - dev->command |= PCI_COMMAND_IO; - dev->command |= PCI_COMMAND_MEMORY; - } - pci_dev_enable_resources(dev); -} - - -static void pcie_scan_bridge(struct device *dev) -{ - u16 val; - u16 ctl; - int flag = 0; - do { - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); - if ((val & (1<<11)) && (!flag)) { /* training error */ - ctl = pci_read_config16(dev, 0x74); - pci_write_config16(dev, 0x74, (ctl | (1<<5))); - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); - flag = 1; - hard_reset(); - } - } while (val & (3<<10)); - - pciexp_scan_bridge(dev); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pcie_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver_0 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0, -}; - -static const struct pci_driver pci_driver_1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1, -}; diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c deleted file mode 100644 index aebe4e864b..0000000000 --- a/src/northbridge/intel/i3100/raminit.c +++ /dev/null @@ -1,1201 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include "raminit.h" -#include "i3100.h" - -/* DDR2 memory controller register space */ -#define MCBAR ((u8 *)(0x90000000)) - -static void sdram_set_registers(const struct mem_controller *ctrl) -{ - static const u32 register_values[] = { - - /* CKDIS 0x8c disable clocks */ - PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - - /* 0x9c Device present and extended RAM control - * DEVPRES is very touchy, hard code the initialization - * of PCI-E ports here. - */ - PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG, - - /* 0xc8 Remap RAM base and limit off */ - PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000, - - /* ??? */ - PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000, - PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a, - - /* 0x50 scrub */ - PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */ - - /* 0x58 0x5c PAM */ - PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000, - PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, - - /* 0xf4 */ - PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG, - - /* 0x14 */ - PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, (uintptr_t)(MCBAR + 0), - }; - int i; - int max; - - max = ARRAY_SIZE(register_values); - for (i = 0; i < max; i += 3) { - device_t dev; - u32 where; - u32 reg; - dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } - printk(BIOS_SPEW, "done.\n"); -} - -struct dimm_size { - u32 side1; - u32 side2; -}; - -static struct dimm_size spd_get_dimm_size(u16 device) -{ - /* Calculate the log base 2 size of a DIMM in bits */ - struct dimm_size sz; - int value, low; - sz.side1 = 0; - sz.side2 = 0; - - /* Note it might be easier to use byte 31 here, it has the DIMM size as - * a multiple of 4MB. The way we do it now we can size both - * sides of an asymmetric dimm. - */ - value = spd_read_byte(device, 3); /* rows */ - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - sz.side1 += value & 0xf; - - value = spd_read_byte(device, 4); /* columns */ - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - sz.side1 += value & 0xf; - - value = spd_read_byte(device, 17); /* banks */ - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - sz.side1 += log2(value & 0xff); - - /* Get the module data width and convert it to a power of two */ - value = spd_read_byte(device, 7); /* (high byte) */ - if (value < 0) goto hw_err; - value &= 0xff; - value <<= 8; - - low = spd_read_byte(device, 6); /* (low byte) */ - if (low < 0) goto hw_err; - value = value | (low & 0xff); - if ((value != 72) && (value != 64)) goto val_err; - sz.side1 += log2(value); - - /* side 2 */ - value = spd_read_byte(device, 5); /* number of physical banks */ - - if (value < 0) goto hw_err; - value &= 7; - value++; - if (value == 1) goto out; - if (value != 2) goto val_err; - - /* Start with the symmetrical case */ - sz.side2 = sz.side1; - - value = spd_read_byte(device, 3); /* rows */ - if (value < 0) goto hw_err; - if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */ - sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */ - sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */ - - value = spd_read_byte(device, 4); /* columns */ - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */ - sz.side2 += ((value >> 4) & 0x0f); /* Add in columns on side 2 */ - goto out; - - val_err: - die("Bad SPD value\n"); - /* If an hw_error occurs report that I have no memory */ - hw_err: - sz.side1 = 0; - sz.side2 = 0; -out: - return sz; - -} - -static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask) -{ - int i; - int cum; - - for (i = cum = 0; i < DIMM_SOCKETS; i++) { - struct dimm_size sz; - if (dimm_mask & (1 << i)) { - sz = spd_get_dimm_size(ctrl->channel0[i]); - if (sz.side1 < 29) { - return -1; /* Report SPD error */ - } - /* convert bits to multiples of 64MB */ - sz.side1 -= 29; - cum += (1 << sz.side1); - /* DRB = 0x60 */ - pci_write_config8(ctrl->f0, DRB + (i*2), cum); - if ( sz.side2 > 28) { - sz.side2 -= 29; - cum += (1 << sz.side2); - } - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); - } - else { - pci_write_config8(ctrl->f0, DRB + (i*2), cum); - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); - } - } - cum >>= 1; - /* set TOM top of memory 0xcc */ - pci_write_config16(ctrl->f0, TOM, cum); - /* set TOLM top of low memory */ - if (cum > 0x18) { - cum = 0x18; - } - cum <<= 11; - /* 0xc4 TOLM */ - pci_write_config16(ctrl->f0, TOLM, cum); - return 0; -} - - -static u32 spd_detect_dimms(const struct mem_controller *ctrl) -{ - u32 dimm_mask; - int i; - dimm_mask = 0; - for (i = 0; i < DIMM_SOCKETS; i++) { - int byte; - u16 device; - device = ctrl->channel0[i]; - if (device) { - byte = spd_read_byte(device, 2); /* Type */ - if (byte == 8) { - dimm_mask |= (1 << i); - } - } - device = ctrl->channel1[i]; - if (device) { - byte = spd_read_byte(device, 2); - if (byte == 8) { - dimm_mask |= (1 << (i + DIMM_SOCKETS)); - } - } - } - return dimm_mask; -} - - -static int spd_set_row_attributes(const struct mem_controller *ctrl, - long dimm_mask) -{ - int value; - int reg; - int dra; - int cnt; - - dra = 0; - for (cnt = 0; cnt < 4; cnt++) { - if (!(dimm_mask & (1 << cnt))) { - continue; - } - reg =0; - value = spd_read_byte(ctrl->channel0[cnt], 3); /* rows */ - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - reg += value & 0xf; - - value = spd_read_byte(ctrl->channel0[cnt], 4); /* columns */ - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - reg += value & 0xf; - - value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */ - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - reg += log2(value & 0xff); - - /* Get the device width and convert it to a power of two */ - value = spd_read_byte(ctrl->channel0[cnt], 13); - if (value < 0) goto hw_err; - value = log2(value & 0xff); - reg += value; - if (reg < 27) goto hw_err; - reg -= 27; - reg += (value << 2); - - dra += reg << (cnt*8); - value = spd_read_byte(ctrl->channel0[cnt], 5); - if (value & 2) - dra += reg << ((cnt*8)+4); - } - - /* 0x70 DRA */ - pci_write_config32(ctrl->f0, DRA, dra); - goto out; - - val_err: - die("Bad SPD value\n"); - /* If an hw_error occurs report that I have no memory */ - hw_err: - dra = 0; -out: - return dra; - -} - - -static int spd_set_drt_attributes(const struct mem_controller *ctrl, - long dimm_mask, u32 drc) -{ - int value; - int reg; - u32 drt; - int cnt; - int first_dimm; - int cas_latency = 0; - int latency; - u32 index = 0; - u32 index2 = 0; - static const u8 cycle_time[3] = { 0x75, 0x60, 0x50 }; - static const u8 latency_indicies[] = { 26, 23, 9 }; - - /* 0x78 DRT */ - drt = pci_read_config32(ctrl->f0, DRT); - drt &= 3; /* save bits 1:0 */ - - for (first_dimm = 0; first_dimm < 4; first_dimm++) { - if (dimm_mask & (1 << first_dimm)) - break; - } - - drt |= (1<<6); /* back to back write turn around */ - - drt |= (3<<18); /* Trasmax */ - - for (cnt = 0; cnt < 4; cnt++) { - if (!(dimm_mask & (1 << cnt))) { - continue; - } - reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */ - /* Compute the lowest cas latency supported */ - latency = log2(reg) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - if ((latency < 2) || (latency > 4) || - (!(reg & (1 << latency)))) { - continue; - } - value = spd_read_byte(ctrl->channel0[cnt], - latency_indicies[index]); - - if (value <= cycle_time[drc & 3]) { - if ( latency > cas_latency) { - cas_latency = latency; - } - break; - } - } - } - index = (cas_latency-2); - if ((index) == 0) cas_latency = 20; - else if ((index) == 1) cas_latency = 25; - else cas_latency = 30; - - for (cnt = 0; cnt < 4; cnt++) { - if (!(dimm_mask & (1 << cnt))) { - continue; - } - reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff; - if (((index>>8) & 0x0ff) < reg) { - index &= ~(0x0ff << 8); - index |= (reg << 8); - } - reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff; - if (((index>>16) & 0x0ff) < reg) { - index &= ~(0x0ff << 16); - index |= (reg<<16); - } - reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff; - if (((index2>>0) & 0x0ff) < reg) { - index2 &= ~(0x0ff << 0); - index2 |= (reg<<0); - } - reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff; - if (((index2>>8) & 0x0ff) < reg) { - index2 &= ~(0x0ff << 8); - index2 |= (reg<<8); - } - reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff; - if (((index2>>16) & 0x0ff) < reg) { - index2 &= ~(0x0ff << 16); - index2 |= (reg<<16); - } - } - - /* get dimm speed */ - value = cycle_time[drc & 3]; - if (value <= 0x50) { /* 200 MHz */ - if ((index & 7) > 2) { - drt |= (2<<2); /* CAS latency 4 */ - cas_latency = 40; - } else { - drt |= (1<<2); /* CAS latency 3 */ - cas_latency = 30; - } - if ((index & 0x0ff00) <= 0x03c00) { - drt |= (1<<8); /* Trp RAS Precharge */ - } else { - drt |= (2<<8); /* Trp RAS Precharge */ - } - - /* Trcd RAS to CAS delay */ - if ((index2 & 0x0ff) <= 0x03c) { - drt |= (0<<10); - } else { - drt |= (1<<10); - } - - /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); - - /* Trc TRS min */ - if ((index2 & 0x0ff00) <= 0x03700) - drt |= (0<<14); - else if ((index2 & 0xff00) <= 0x03c00) - drt |= (1<<14); - else - drt |= (2<<14); /* spd 41 */ - - drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */ - - /* Trrd Row Delay */ - if ((index & 0x0ff0000) <= 0x0140000) { - drt |= (0<<20); - } else if ((index & 0x0ff0000) <= 0x0280000) { - drt |= (1<<20); - } else if ((index & 0x0ff0000) <= 0x03c0000) { - drt |= (2<<20); - } else { - drt |= (3<<20); - } - - /* Trfc Auto refresh cycle time */ - if ((index2 & 0x0ff0000) <= 0x04b0000) { - drt |= (0<<22); - } else if ((index2 & 0x0ff0000) <= 0x0690000) { - drt |= (1<<22); - } else { - drt |= (2<<22); - } - /* Docs say use 55 for all 200MHz */ - drt |= (0x055<<24); - } - else if (value <= 0x60) { /* 167 MHz */ - /* according to new documentation CAS latency is 00 - * for bits 3:2 for all 167 MHz - drt |= ((index & 3)<<2); */ /* set CAS latency */ - if ((index & 0x0ff00) <= 0x03000) { - drt |= (1<<8); /* Trp RAS Precharge */ - } else { - drt |= (2<<8); /* Trp RAS Precharge */ - } - - /* Trcd RAS to CAS delay */ - if ((index2 & 0x0ff) <= 0x030) { - drt |= (0<<10); - } else { - drt |= (1<<10); - } - - /* Tdal Write auto precharge recovery delay */ - drt |= (2<<12); - - /* Trc TRS min */ - drt |= (2<<14); /* spd 41, but only one choice */ - - drt |= (2<<16); /* Twr not defined for DDR docs say 2 */ - - /* Trrd Row Delay */ - if ((index & 0x0ff0000) <= 0x0180000) { - drt |= (0<<20); - } else if ((index & 0x0ff0000) <= 0x0300000) { - drt |= (1<<20); - } else { - drt |= (2<<20); - } - - /* Trfc Auto refresh cycle time */ - if ((index2 & 0x0ff0000) <= 0x0480000) { - drt |= (0<<22); - } else if ((index2 & 0x0ff0000) <= 0x0780000) { - drt |= (2<<22); - } else { - drt |= (2<<22); - } - /* Docs state to use 99 for all 167 MHz */ - drt |= (0x099<<24); - } - else if (value <= 0x75) { /* 133 MHz */ - drt |= ((index & 3)<<2); /* set CAS latency */ - if ((index & 0x0ff00) <= 0x03c00) { - drt |= (1<<8); /* Trp RAS Precharge */ - } else { - drt |= (2<<8); /* Trp RAS Precharge */ - } - - /* Trcd RAS to CAS delay */ - if ((index2 & 0x0ff) <= 0x03c) { - drt |= (0<<10); - } else { - drt |= (1<<10); - } - - /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); - - /* Trc TRS min */ - drt |= (2<<14); /* spd 41, but only one choice */ - - drt |= (1<<16); /* Twr not defined for DDR docs say 1 */ - - /* Trrd Row Delay */ - if ((index & 0x0ff0000) <= 0x01e0000) { - drt |= (0<<20); - } else if ((index & 0x0ff0000) <= 0x03c0000) { - drt |= (1<<20); - } else { - drt |= (2<<20); - } - - /* Trfc Auto refresh cycle time */ - if ((index2 & 0x0ff0000) <= 0x04b0000) { - drt |= (0<<22); - } else if ((index2 & 0x0ff0000) <= 0x0780000) { - drt |= (2<<22); - } else { - drt |= (2<<22); - } - - /* Based on CAS latency */ - if (index & 7) - drt |= (0x099<<24); - else - drt |= (0x055<<24); - - } - else { - die("Invalid SPD 9 bus speed.\n"); - } - - /* 0x78 DRT */ - pci_write_config32(ctrl->f0, DRT, drt); - - return(cas_latency); -} - -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, - long dimm_mask) -{ - int value; - int drc; - int cnt; - msr_t msr; - u8 rate = 62; - static const u8 spd_rates[6] = {15,3,7,7,62,62}; - static const u8 drc_rates[5] = {0,15,7,62,3}; - static const u8 fsb_conversion[8] = {0,1,3,2,3,0,3,3}; - - /* 0x7c DRC */ - drc = pci_read_config32(ctrl->f0, DRC); - for (cnt = 0; cnt < 4; cnt++) { - if (!(dimm_mask & (1 << cnt))) { - continue; - } - value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */ - if (value != 2) die("ERROR - Non ECC memory dimm\n"); - - value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/ - value &= 0x0f; /* clip self refresh bit */ - if (value > 5) goto hw_err; - if (rate > spd_rates[value]) - rate = spd_rates[value]; - - value = spd_read_byte(ctrl->channel0[cnt], 9); /* cycle time */ - if (value > 0x75) goto hw_err; - } - drc |= (1 << 20); /* enable ECC */ - for (cnt = 1; cnt < 5; cnt++) - if (drc_rates[cnt] == rate) - break; - if (cnt < 5) { - drc &= ~(7 << 8); /* clear the rate bits */ - drc |= (cnt << 8); - } - - drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */ - drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */ - drc |= (1 << 7); - drc &= ~(1 << 5); /* enable ODT */ - drc |= (1 << 4); /* independent clocks */ - - /* set front side bus speed */ - msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */ - value = msr.lo & 0x07; - drc &= ~(3 << 2); - drc |= (fsb_conversion[value] << 2); - - /* set dram type to ddr2 */ - drc &= ~(3 << 0); - drc |= (2 << 0); - - goto out; - - /* If an hw_error occurs report that I have no memory */ - hw_err: - drc = 0; -out: - return drc; -} - -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - long dimm_mask; - - /* Test if we can read the spd and if RAM is ddr or ddr2 */ - dimm_mask = spd_detect_dimms(ctrl); - if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - printk(BIOS_ERR, "No memory for this cpu\n"); - return; - } - return; -} - -static void do_delay(void) -{ - int i; - u8 b; - for (i = 0; i < 16; i++) - b = inb(0x80); -} - -#define TIMEOUT_LOOPS 300000 - -#define DCALCSR 0x100 -#define DCALADDR 0x104 -#define DCALDATA 0x108 - -static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) -{ - u8 c1,c2; - u32 dimm,i; - u32 data32 = 0; - u32 t4; - - /* Set up northbridge values */ - /* ODT enable */ - pci_write_config32(ctrl->f0, SDRC, 0x30000000); - /* Figure out which slots are Empty, Single, or Double sided */ - for (i = 0,t4 = 0,c2 = 0; i < 8; i+=2) { - c1 = pci_read_config8(ctrl->f0, DRB+i); - if (c1 == c2) continue; - c2 = pci_read_config8(ctrl->f0, DRB+1+i); - if (c1 == c2) - t4 |= (1 << (i*4)); - else - t4 |= (2 << (i*4)); - } - for (i = 0; i < 1; i++) { - if ((t4 & 0x0f) == 1) { - if ( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00000010; /* EEES */ - break; - } - if ( ((t4>>16)&0x0f) == 0 ) { - data32 = 0x00003132; /* EESS */ - break; - } - if ( ((t4>>24)&0x0f) == 0 ) { - data32 = 0x00335566; /* ESSS */ - break; - } - data32 = 0x77bbddee; /* SSSS */ - break; - } - if ((t4 & 0x0f) == 2) { - if ( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00003132; /* EEED */ - break; - } - if ( ((t4>>8)&0x0f) == 2 ) { - data32 = 0xb373ecdc; /* EEDD */ - break; - } - if ( ((t4>>16)&0x0f) == 0 ) { - data32 = 0x00b3a898; /* EESD */ - break; - } - data32 = 0x777becdc; /* ESSD */ - break; - } - die("Error - First dimm slot empty\n"); - } - - printk(BIOS_DEBUG, "ODT Value = %08x\n", data32); - - pci_write_config32(ctrl->f0, DDR2ODTC, data32); - - for (dimm = 0;dimm < 8;dimm+=2) { - - write32(MCBAR+DCALADDR, 0x0b840001); - write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20)); - - for (i = 0; i < 1001; i++) { - data32 = read32(MCBAR+DCALCSR); - if (!(data32 & (1<<31))) - break; - } - } -} -static void set_receive_enable(const struct mem_controller *ctrl) -{ - u32 i; - u32 cnt; - u32 recena = 0; - u32 recenb = 0; - - { - u32 dimm; - u32 edge; - int32_t data32; - u32 dcal_data32_0; - u32 dcal_data32_1; - u32 dcal_data32_2; - u32 dcal_data32_3; - u32 work32l; - u32 work32h; - u32 data32r; - int32_t recen; - for (dimm = 0;dimm < 8;dimm+=1) { - - if (!(dimm & 1)) { - write32(MCBAR+DCALDATA+(17*4), 0x04020000); - write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20)); - - for (i = 0; i < 1001; i++) { - data32 = read32(MCBAR+DCALCSR); - if (!(data32 & (1<<31))) - break; - } - if (i >= 1000) - continue; - - dcal_data32_0 = read32(MCBAR+DCALDATA + 0); - dcal_data32_1 = read32(MCBAR+DCALDATA + 4); - dcal_data32_2 = read32(MCBAR+DCALDATA + 8); - dcal_data32_3 = read32(MCBAR+DCALDATA + 12); - } - else { - dcal_data32_0 = read32(MCBAR+DCALDATA + 16); - dcal_data32_1 = read32(MCBAR+DCALDATA + 20); - dcal_data32_2 = read32(MCBAR+DCALDATA + 24); - dcal_data32_3 = read32(MCBAR+DCALDATA + 28); - } - - /* check if bank is installed */ - if ((dcal_data32_0 == 0) && (dcal_data32_2 == 0)) - continue; - /* Calculate the timing value */ - { - u32 bit; - for (i = 0,edge = 0,bit = 63,cnt = 31,data32r = 0, - work32l = dcal_data32_1,work32h = dcal_data32_3; - (i < 4) && bit; i++) { - for (;;bit--,cnt--) { - if (work32l & (1< 12) { - if (!edge) { - edge = 2; - } - else { - if (edge != 2) { - data32 = 0x00; - } - } - } - data32r += data32; - } - } - work32l = dcal_data32_0; - work32h = dcal_data32_2; - recen = data32r; - recen += 3; - recen = recen>>2; - for (cnt = 5; cnt < 24;) { - for (;; cnt++) - if (!(work32l & (1< 12) && - (((recen+16)-data32) < 3)) { - data32 = 0; - cnt += 2; - } - if ((edge == 2) && (data32 < 4) && - ((recen - data32) > 12)) { - data32 = 0x0f; - cnt -= 2; - } - if (((recen+3) >= data32) && ((recen-3) <= data32)) - break; - } - cnt--; - cnt /= 8; - cnt--; - if (recen & 1) - recen+=2; - recen >>= 1; - recen += (cnt*8); - recen+=2; /* this is not in the spec, but matches - the factory output, and has less failure */ - recen <<= (dimm/2) * 8; - if (!(dimm & 1)) { - recena |= recen; - } - else { - recenb |= recen; - } - } - } - /* Check for Errata problem */ - for (i = cnt = 0; i < 32; i+=8) { - if (((recena>>i)&0x0f)>7) { - cnt+= 0x101; - } - else { - if ((recena>>i)&0x0f) { - cnt++; - } - } - } - if (cnt & 0x0f00) { - cnt = (cnt & 0x0f) - (cnt>>16); - if (cnt > 1) { - for (i = 0; i < 32; i+=8) { - if (((recena>>i)&0x0f)>7) { - recena &= ~(0x0f<>i)&0x0f)<8) { - recena &= ~(0x0f<>i)&0x0f)>7) { - cnt+= 0x101; - } - else { - if ((recenb>>i)&0x0f) { - cnt++; - } - } - } - if (cnt & 0x0f00) { - cnt = (cnt & 0x0f) - (cnt>>16); - if (cnt > 1) { - for (i = 0; i < 32; i+=8) { - if (((recenb>>i)&0x0f)>7) { - recenb &= ~(0x0f<>8)&0x0f)<8) { - recenb &= ~(0x0f<f0, DRM, - 0x00410000 | CONFIG_DIMM_MAP_LOGICAL); - /* set dram type and Front Side Bus freq. */ - drc = spd_set_dram_controller_mode(ctrl, mask); - if ( drc == 0) { - die("Error calculating DRC\n"); - } - data32 = drc & ~(3 << 20); /* clear ECC mode */ - data32 = data32 & ~(7 << 8); /* clear refresh rates */ - data32 = data32 | (1 << 5); /* temp turn off ODT */ - /* Set gearing, then dram controller mode */ - /* drc bits 3:2 = FSB speed */ - for (iptr = gearing[(drc>>2)&3].clkgr,cnt = 0; cnt < 4; cnt++) { - pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]); - } - /* 0x7c DRC */ - pci_write_config32(ctrl->f0, DRC, data32); - - /* turn the clocks on */ - /* 0x8c CKDIS */ - pci_write_config16(ctrl->f0, CKDIS, 0x0000); - - /* 0x9a DDRCSR Take subsystem out of idle */ - data16 = pci_read_config16(ctrl->f0, DDRCSR); - data16 &= ~(7 << 12); - data16 |= (1 << 12); - pci_write_config16(ctrl->f0, DDRCSR, data16); - - /* program row size DRB */ - spd_set_ram_size(ctrl, mask); - - /* program page size DRA */ - spd_set_row_attributes(ctrl, mask); - - /* program DRT timing values */ - cas_latency = spd_set_drt_attributes(ctrl, mask, drc); - - for (i = 0; i < 8; i+=2) { /* loop through each dimm to test */ - printk(BIOS_DEBUG, "DIMM %08x\n", i); - /* Apply NOP */ - do_delay(); - - write32(MCBAR+DCALCSR, (0x01000000 | (i<<20))); - write32(MCBAR+DCALCSR, (0x81000000 | (i<<20))); - - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Apply NOP */ - do_delay(); - - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Precharge all banks */ - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALADDR, 0x04000000); - write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* EMRS dll's enabled */ - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - /* fixme hard code AL additive latency */ - write32(MCBAR+DCALADDR, 0x0b940001); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - /* MRS reset dll's */ - do_delay(); - if (cas_latency == 30) - mode_reg = 0x053a0000; - else - mode_reg = 0x054a0000; - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALADDR, mode_reg); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Precharge all banks */ - do_delay(); - do_delay(); - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALADDR, 0x04000000); - write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Do 2 refreshes */ - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - do_delay(); - /* for good luck do 6 more */ - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - /* MRS reset dll's normal */ - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24))); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Do only if DDR2 EMRS dll's enabled */ - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALADDR, (0x0b940001)); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - do_delay(); - /* No command */ - write32(MCBAR+DCALCSR, 0x0000000f); - - /* enable on dimm termination */ - set_on_dimm_termination_enable(ctrl); - - /* receive enable calibration */ - set_receive_enable(ctrl); - - /* DQS */ - pci_write_config32(ctrl->f0, 0x94, 0x3904aa00); - for (i = 0, cntptr = (MCBAR+0x200); i < 24; i++, cnt+=4) { - write32(cntptr, dqs_data[i]); - } - pci_write_config32(ctrl->f0, 0x94, 0x3900aa00); - - /* Enable refresh */ - /* 0x7c DRC */ - data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); - write32(MCBAR+DCALCSR, 0x0008000f); - - /* clear memory and init ECC */ - printk(BIOS_DEBUG, "Clearing memory\n"); - for (i = 0; i < 64; i+=4) { - write32(MCBAR+DCALDATA+i, 0x00000000); - } - - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Bring memory subsystem on line */ - data32 = pci_read_config32(ctrl->f0, 0x98); - data32 |= (1 << 31); - pci_write_config32(ctrl->f0, 0x98, data32); - /* wait for completion */ - printk(BIOS_DEBUG, "Waiting for mem complete\n"); - while (1) { - data32 = pci_read_config32(ctrl->f0, 0x98); - if ( (data32 & (1<<31)) == 0) - break; - } - printk(BIOS_DEBUG, "Done\n"); - - /* Set initialization complete */ - /* 0x7c DRC */ - drc |= (1 << 29); - data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); - - /* Set the ecc mode */ - pci_write_config32(ctrl->f0, DRC, drc); - - /* Enable memory scrubbing */ - /* 0x52 MCHSCRB */ - data16 = pci_read_config16(ctrl->f0, MCHSCRB); - data16 &= ~0x0f; - data16 |= ((2 << 2) | (2 << 0)); - pci_write_config16(ctrl->f0, MCHSCRB, data16); - - /* The memory is now setup, use it */ - if (!IS_ENABLED(CONFIG_CACHE_AS_RAM)) - cache_ramstage(); -} diff --git a/src/northbridge/intel/i3100/raminit.h b/src/northbridge/intel/i3100/raminit.h deleted file mode 100644 index aa245deba5..0000000000 --- a/src/northbridge/intel/i3100/raminit.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This code is based on src/northbridge/intel/e7520/raminit.h */ - -#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_H -#define NORTHBRIDGE_INTEL_I3100_RAMINIT_H - -#define DIMM_SOCKETS 4 -struct mem_controller { - u32 node_id; - device_t f0, f1, f2, f3; - u16 channel0[DIMM_SOCKETS]; - u16 channel1[DIMM_SOCKETS]; -}; - -void sdram_initialize(int controllers, const struct mem_controller *ctrl); - -#endif diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c deleted file mode 100644 index fa557da0f1..0000000000 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ /dev/null @@ -1,693 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "raminit_ep80579.h" -#include "ep80579.h" - -#define BAR ((u8 *)0x90000000) - -static void sdram_set_registers(const struct mem_controller *ctrl) -{ - static const u32 register_values[] = { - PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420001 | DEVPRES_CONFIG, - PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000, - PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, - PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a, - PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, (uintptr_t)BAR | 0, - }; - int i; - - for (i = 0; i < ARRAY_SIZE(register_values); i += 3) { - device_t dev; - u32 where; - u32 reg; - dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } -} - -struct dimm_size { - u32 side1; - u32 side2; -}; - -static struct dimm_size spd_get_dimm_size(u16 device) -{ - /* Calculate the log base 2 size of a DIMM in bits */ - struct dimm_size sz; - int value, low; - sz.side1 = 0; - sz.side2 = 0; - - /* Note it might be easier to use byte 31 here, it has the DIMM size as - * a multiple of 4MB. The way we do it now we can size both - * sides of an assymetric dimm. - */ - value = spd_read_byte(device, SPD_NUM_ROWS); - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - sz.side1 += value & 0xf; - - value = spd_read_byte(device, SPD_NUM_COLUMNS); - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - sz.side1 += value & 0xf; - - value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - sz.side1 += log2(value & 0xff); - - /* Get the module data width and convert it to a power of two */ - value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); - if (value < 0) goto hw_err; - value &= 0xff; - value <<= 8; - - low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); - if (low < 0) goto hw_err; - value = value | (low & 0xff); - if ((value != 72) && (value != 64)) goto val_err; - sz.side1 += log2(value); - - /* side 2 */ - value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); - - if (value < 0) goto hw_err; - value &= 7; - value++; - if (value == 1) goto out; - if (value != 2) goto val_err; - - /* Start with the symmetrical case */ - sz.side2 = sz.side1; - - value = spd_read_byte(device, SPD_NUM_ROWS); - if (value < 0) goto hw_err; - if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */ - sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */ - sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */ - - value = spd_read_byte(device, SPD_NUM_COLUMNS); - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */ - sz.side2 += ((value >> 4) & 0x0f); /* Add in columns on side 2 */ - goto out; - - val_err: - die("Bad SPD value\n"); - /* If an hw_error occurs report that I have no memory */ - hw_err: - sz.side1 = 0; - sz.side2 = 0; -out: - printk(BIOS_DEBUG, "dimm %02x size = %02x.%02x\n", device, sz.side1, sz.side2); - return sz; - -} - -static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask) -{ - int i; - int cum; - - for (i = cum = 0; i < DIMM_SOCKETS; i++) { - struct dimm_size sz; - if (dimm_mask & (1 << i)) { - sz = spd_get_dimm_size(ctrl->channel0[i]); - if (sz.side1 < 29) { - return -1; /* Report SPD error */ - } - /* convert bits to multiples of 64MB */ - sz.side1 -= 29; - cum += (1 << sz.side1); - pci_write_config8(ctrl->f0, DRB + (i*2), cum); - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); - if (spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS) & 0x1) { - cum <<= 1; - } - } - else { - pci_write_config8(ctrl->f0, DRB + (i*2), cum); - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); - } - } - printk(BIOS_DEBUG, "DRB = %08x\n", pci_read_config32(ctrl->f0, DRB)); - - cum >>= 1; - /* set TOM top of memory */ - pci_write_config16(ctrl->f0, TOM, cum); - printk(BIOS_DEBUG, "TOM = %04x\n", cum); - /* set TOLM top of low memory */ - if (cum > 0x18) { - cum = 0x18; - } - cum <<= 11; - pci_write_config16(ctrl->f0, TOLM, cum); - printk(BIOS_DEBUG, "TOLM = %04x\n", cum); - return 0; -} - - -static u8 spd_detect_dimms(const struct mem_controller *ctrl) -{ - u8 dimm_mask = 0; - int i; - for (i = 0; i < DIMM_SOCKETS; i++) { - int byte; - u16 device; - device = ctrl->channel0[i]; - if (device) { - byte = spd_read_byte(device, SPD_MEMORY_TYPE); - printk(BIOS_DEBUG, "spd %02x = %02x\n", device, byte); - if (byte == 8) { - dimm_mask |= (1 << i); - } - } - } - return dimm_mask; -} - - -static int spd_set_row_attributes(const struct mem_controller *ctrl, - u8 dimm_mask) -{ - int value; - int i; - - for (i = 0; i < DIMM_SOCKETS; i++) { - u32 dra = 0; - int reg = 0; - - if (!(dimm_mask & (1 << i))) { - continue; - } - - value = spd_read_byte(ctrl->channel0[i], SPD_NUM_ROWS); - if (value < 0) die("Bad SPD data\n"); - if ((value & 0xf) == 0) die("Invalid # of rows\n"); - dra |= (((value-13) & 0x7) << 23); - dra |= (((value-13) & 0x7) << 29); - reg += value & 0xf; - - value = spd_read_byte(ctrl->channel0[i], SPD_NUM_COLUMNS); - if (value < 0) die("Bad SPD data\n"); - if ((value & 0xf) == 0) die("Invalid # of columns\n"); - dra |= (((value-10) & 0x7) << 20); - dra |= (((value-10) & 0x7) << 26); - reg += value & 0xf; - - value = spd_read_byte(ctrl->channel0[i], SPD_NUM_BANKS_PER_SDRAM); - if (value < 0) die("Bad SPD data\n"); - if ((value & 0xff) == 0) die("Invalid # of banks\n"); - reg += log2(value & 0xff); - - printk(BIOS_DEBUG, "dimm %02x reg = %02x\n", i, reg); - - /* set device density */ - dra |= ((31-reg)); - dra |= ((31-reg) << 6); - - /* set device width (x8) */ - dra |= (1 << 4); - dra |= (1 << 10); - - /* set device type (registered) */ - dra |= (1 << 14); - - /* set number of ranks (0 = single, 1 = dual) */ - value = spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS); - dra |= ((value & 0x1) << 17); - - printk(BIOS_DEBUG, "DRA%02x = %08x\n", i, dra); - - pci_write_config32(ctrl->f0, DRA + (i*4), dra); - } - return 0; -} - - -static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, - u8 dimm_mask, u32 drc) -{ - int i; - u32 val, val1; - u32 cl; - u32 trc = 0; - u32 trfc = 0; - u32 tras = 0; - u32 trtp = 0; - u32 twtr = 0; - int index = drc & 0x00000003; - int ci; - static const u8 latencies[] = { /* 533, 800, 400, 667 */ - 0x10, 0x60, 0x10, 0x20 }; - static const u32 drt0[] = { /* 533, 800, 400, 667 */ - 0x24240002, 0x24360002, 0x24220002, 0x24360002 }; - static const u32 drt1[] = { /* 533, 800, 400, 667 */ - 0x00400000, 0x00900000, 0x00200000, 0x00700000 }; - static const u32 magic[] = { /* 533, 800, 400, 667 */ - 0x007b8221, 0x00b94331, 0x005ca1a1, 0x009a62b1 }; - static const u32 mrs[] = { /* 533, 800, 400, 667 */ - 0x07020000, 0x0b020000, 0x05020000, 0x09020000 }; - static const int cycle[] = { /* 533, 800, 400, 667 */ - 15, 10, 20, 12 }; /* cycle time in 1/4 ns units */ - static const int byte40rem[] = { - 0, 1, 2, 2, 3, 3, 0, 0 }; /* byte 40 remainder in 1/4 ns units */ - - /* CAS latency in cycles */ - val = latencies[index]; - for (i = 0; i < DIMM_SOCKETS; i++) { - if (!(dimm_mask & (1 << i))) - continue; - val &= spd_read_byte(ctrl->channel0[i], SPD_ACCEPTABLE_CAS_LATENCIES); - } - if (val & 0x10) - cl = 4; - else if (val & 0x20) - cl = 5; - else if (val & 0x40) - cl = 6; - else - die("CAS latency mismatch\n"); - printk(BIOS_DEBUG, "cl = %02x\n", cl); - - ci = cycle[index]; - - /* Trc, Trfc in cycles */ - for (i = 0; i < DIMM_SOCKETS; i++) { - if (!(dimm_mask & (1 << i))) - continue; - val1 = spd_read_byte(ctrl->channel0[i], SPD_BYTE_41_42_EXTENSION); - val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACT_TO_ACT_AUTO_REFRESH); - val <<= 2; /* convert to 1/4 ns */ - val += byte40rem[(val1 >> 4) & 0x7]; - val = CEIL_DIV(val, ci) + 1; /* convert to cycles */ - if (trc < val) - trc = val; - val = spd_read_byte(ctrl->channel0[i], SPD_MIN_AUTO_REFRESH_TO_ACT); - val <<= 2; /* convert to 1/4 ns */ - if (val1 & 0x01) - val += 1024; - val += byte40rem[(val1 >> 1) & 0x7]; - val = CEIL_DIV(val, ci); /* convert to cycles */ - if (trfc < val) - trfc = val; - } - printk(BIOS_DEBUG, "trc = %02x\n", trc); - printk(BIOS_DEBUG, "trfc = %02x\n", trfc); - - /* Tras, Trtp, Twtr in cycles */ - for (i = 0; i < DIMM_SOCKETS; i++) { - if (!(dimm_mask & (1 << i))) - continue; - val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - val <<= 2; /* convert to 1/4 ns */ - val = CEIL_DIV(val, ci); /* convert to cycles */ - if (tras < val) - tras = val; - val = spd_read_byte(ctrl->channel0[i], SPD_INT_READ_TO_PRECHARGE_DELAY); - val = CEIL_DIV(val, ci); /* convert to cycles */ - if (trtp < val) - trtp = val; - val = spd_read_byte(ctrl->channel0[i], SPD_INT_WRITE_TO_READ_DELAY); - val = CEIL_DIV(val, ci); /* convert to cycles */ - if (twtr < val) - twtr = val; - } - printk(BIOS_DEBUG, "tras = %02x\n", tras); - printk(BIOS_DEBUG, "trtp = %02x\n", trtp); - printk(BIOS_DEBUG, "twtr = %02x\n", twtr); - - val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9) - | ((cl - 3) << 6) | ((cl - 3) << 3)); - printk(BIOS_DEBUG, "drt0 = %08x\n", val); - pci_write_config32(ctrl->f0, DRT0, val); - - val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25) - | (twtr << 15)); - printk(BIOS_DEBUG, "drt1 = %08x\n", val); - pci_write_config32(ctrl->f0, DRT1, val); - - val = (magic[index]); - printk(BIOS_DEBUG, "magic = %08x\n", val); - pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val); - - val = (mrs[index] | (cl << 20)); - printk(BIOS_DEBUG, "mrs = %08x\n", val); - return val; -} - -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, - u8 dimm_mask) -{ - int value; - int drc = 0; - int i; - msr_t msr; - u8 cycle = 0x25; - - for (i = 0; i < DIMM_SOCKETS; i++) { - if (!(dimm_mask & (1 << i))) - continue; - if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40) - die("ERROR: Only 64-bit DIMMs supported\n"); - if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02)) - die("ERROR: Only ECC DIMMs supported\n"); - if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08) - die("ERROR: Only x8 DIMMs supported\n"); - - value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - if (value > cycle) - cycle = value; - } - printk(BIOS_DEBUG, "cycle = %02x\n", cycle); - - drc |= (1 << 20); /* enable ECC */ - drc |= (3 << 30); /* enable CKE on each DIMM */ - drc |= (1 << 4); /* enable CKE globally */ - - /* TODO check: */ - /* set front side bus speed */ - msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */ - printk(BIOS_DEBUG, "MSR FSB_FREQ(0xcd) = %08x%08x\n", msr.hi, msr.lo); - - /* TODO check that this msr really indicates fsb speed! */ - if (msr.lo & 0x07) { - printk(BIOS_INFO, "533 MHz FSB\n"); - if (cycle <= 0x25) { - drc |= 0x5; - printk(BIOS_INFO, "400 MHz DDR\n"); - } else if (cycle <= 0x30) { - drc |= 0x7; - printk(BIOS_INFO, "333 MHz DDR\n"); - } else if (cycle <= 0x3d) { - drc |= 0x4; - printk(BIOS_INFO, "266 MHz DDR\n"); - } else { - drc |= 0x2; - printk(BIOS_INFO, "200 MHz DDR\n"); - } - } - else { - printk(BIOS_INFO, "400 MHz FSB\n"); - if (cycle <= 0x30) { - drc |= 0x7; - printk(BIOS_INFO, "333 MHz DDR\n"); - } else if (cycle <= 0x3d) { - drc |= 0x0; - printk(BIOS_INFO, "266 MHz DDR\n"); - } else { - drc |= 0x2; - printk(BIOS_INFO, "200 MHz DDR\n"); - } - } - - printk(BIOS_DEBUG, "DRC = %08x\n", drc); - - return drc; -} - -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - u8 dimm_mask; - - /* Test if we can read the SPD */ - dimm_mask = spd_detect_dimms(ctrl); - if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - printk(BIOS_ERR, "No memory for this cpu\n"); - return; - } - return; -} - -static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) -{ - u8 c1,c2; - u32 i; - u32 data32 = 0; - - /* Set up northbridge values */ - /* ODT enable */ - pci_write_config32(ctrl->f0, SDRC, 0xa0002c30); - - c1 = pci_read_config8(ctrl->f0, DRB); - c2 = pci_read_config8(ctrl->f0, DRB+2); - if (c1 == c2) { - /* 1 single-rank DIMM */ - data32 = 0x00000010; - } - else { - /* 2 single-rank DIMMs or 1 double-rank DIMM */ - data32 = 0x00002010; - } - - printk(BIOS_DEBUG, "ODT Value = %08x\n", data32); - - pci_write_config32(ctrl->f0, DDR2ODTC, data32); - - for (i = 0; i < 2; i++) { - printk(BIOS_DEBUG, "ODT CS%d\n", i); - - write32(BAR+DCALADDR, 0x0b840001); - write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21)); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } -} - - -static void dump_dcal_regs(void) -{ - int i; - for (i = 0x0; i < 0x2a0; i += 4) { - if ((i % 16) == 0) { - printk(BIOS_DEBUG, "\n%04x: ", i); - } - printk(BIOS_DEBUG, "%08x ", read32(BAR+i)); - } - printk(BIOS_DEBUG, "\n"); -} - - -static void sdram_enable(int controllers, const struct mem_controller *ctrl) -{ - int i; - int cs; - long mask; - u32 drc; - u32 data32; - u32 mode_reg; - - mask = spd_detect_dimms(ctrl); - printk(BIOS_DEBUG, "Starting SDRAM Enable\n"); - - /* Set DRAM type and Front Side Bus frequency */ - drc = spd_set_dram_controller_mode(ctrl, mask); - if (drc == 0) { - die("Error calculating DRC\n"); - } - data32 = drc & ~(3 << 20); /* clear ECC mode */ - data32 = data32 | (3 << 5); /* temp turn off ODT */ - /* Set DRAM controller mode */ - pci_write_config32(ctrl->f0, DRC, data32); - - /* Turn the clocks on */ - pci_write_config16(ctrl->f0, CKDIS, 0x0000); - - /* Program row size */ - spd_set_ram_size(ctrl, mask); - - /* Program row attributes */ - spd_set_row_attributes(ctrl, mask); - - /* Program timing values */ - mode_reg = spd_set_drt_attributes(ctrl, mask, drc); - - dump_dcal_regs(); - - /* Apply NOP */ - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "NOP CS%d\n", cs); - udelay(16); - write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21))); - write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Apply NOP */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "NOP CS%d\n", cs); - write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Precharge all banks */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "Precharge CS%d\n", cs); - write32(BAR+DCALADDR, 0x04000000); - write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* EMRS: Enable DLLs, set OCD calibration mode to default */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "EMRS CS%d\n", cs); - write32(BAR+DCALADDR, 0x0b840001); - write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - /* MRS: Reset DLLs */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "MRS CS%d\n", cs); - write32(BAR+DCALADDR, mode_reg); - write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Precharge all banks */ - udelay(48); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "Precharge CS%d\n", cs); - write32(BAR+DCALADDR, 0x04000000); - write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Do 2 refreshes */ - for (i = 0; i < 2; i++) { - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "Refresh CS%d\n", cs); - write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - } - - /* MRS: Set DLLs to normal */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "MRS CS%d\n", cs); - write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); - write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* EMRS: Enable DLLs */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "EMRS CS%d\n", cs); - write32(BAR+DCALADDR, 0x0b840001); - write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - udelay(16); - /* No command */ - write32(BAR+DCALCSR, 0x0000000f); - - write32(BAR, 0x00100000); - - /* Enable on-DIMM termination */ - set_on_dimm_termination_enable(ctrl); - - dump_dcal_regs(); - - /* Receive enable calibration */ - udelay(16); - for (cs = 0; cs < 1; cs++) { - printk(BIOS_DEBUG, "receive enable calibration CS%d\n", cs); - write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - dump_dcal_regs(); - - /* Adjust RCOMP */ - data32 = read32(BAR+DDRIOMC2); - data32 &= ~(0xf << 16); - data32 |= (0xb << 16); - write32(BAR+DDRIOMC2, data32); - - dump_dcal_regs(); - - data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); - write32(BAR+DCALCSR, 0x0008000f); - - /* Clear memory and init ECC */ - for (cs = 0; cs < 2; cs++) { - if (!(mask & (1<f0, DRC, data32); - - /* Set the ECC mode */ - pci_write_config32(ctrl->f0, DRC, drc); -} - -static inline int memory_initialized(void) -{ - return pci_read_config32(PCI_DEV(0, 0x00, 0), DRC) & (1 << 29); -} diff --git a/src/northbridge/intel/i3100/raminit_ep80579.h b/src/northbridge/intel/i3100/raminit_ep80579.h deleted file mode 100644 index aca96d2a25..0000000000 --- a/src/northbridge/intel/i3100/raminit_ep80579.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H -#define NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H - -#define DIMM_SOCKETS 2 -struct mem_controller { - u32 node_id; - device_t f0; - u16 channel0[DIMM_SOCKETS]; -}; - -void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif diff --git a/src/northbridge/intel/i3100/reset_test.c b/src/northbridge/intel/i3100/reset_test.c deleted file mode 100644 index 1ea62c0a6c..0000000000 --- a/src/northbridge/intel/i3100/reset_test.c +++ /dev/null @@ -1,20 +0,0 @@ -/* Convert to C by yhlu */ -#define MCH_DRC 0x7c -#define DRC_DONE (1 << 29) - -/* If I have already booted once skip a bunch of initialization */ -/* To see if I have already booted I check to see if memory - * has been enabled. - */ -int bios_reset_detected(void) -{ - uint32_t dword; - - dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - - if ( (dword & DRC_DONE) != 0 ) { - return 1; - } - - return 0; -} -- cgit v1.2.3