From 142b10ee1fa1c68f0c147665ff55b43eb8f0317d Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Mon, 1 Jul 2019 08:54:56 +0300
Subject: cpu/x86: Fix MSR_PLATFORM_INFO definition
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While common to many Intel CPUs, this is not an architectural
MSR that should be globally defined for all x86.

Change-Id: Ibeed022dc2ba2e90f71511f9bd2640a7cafa5292
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
---
 src/northbridge/intel/fsp_rangeley/udelay.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/northbridge/intel')

diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c
index 01989abb37..08301a37f6 100644
--- a/src/northbridge/intel/fsp_rangeley/udelay.c
+++ b/src/northbridge/intel/fsp_rangeley/udelay.c
@@ -18,6 +18,8 @@
 #include <cpu/x86/tsc.h>
 #include <cpu/x86/msr.h>
 
+#define MSR_PLATFORM_INFO 0xce
+
 /**
  * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz
  */
-- 
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