From 12d3768ec5e5d121683d4c47e8fcef0af46c2e21 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 6 Feb 2021 14:39:54 +0100 Subject: nb/intel/pineview: Clean up FIXMEs in raminit Using MCHBAR32_AND_OR() in these two cases changes the order of additions slightly. Originally, the MCHBAR offset and the base register offset (0x5a4/0x5b4) were added first. Due to the added parentheses in the register macros, now the complete register offset is calculated first and then added to MCHBAR. Associativity tells us that this doesn't change the result. Changes in the resulting binary were verified manually on the object file. Change-Id: Id10882225c8e82b02583aa73e73d661c25abdef9 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/50355 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/raminit.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index dd728e8a47..7c6d2b8040 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -916,9 +916,7 @@ static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9); reg32 |= ((u32) pll->dbsel[f][clk]) << dqs; - /* FIXME: Somehow, touching this changes the binary... */ - MCHBAR32(C0DQSRyTX1(rank)) = (MCHBAR32(0x5b4 + (rank * 4)) - & ~((1 << (dqs + 9)) | (1 << dqs))) | reg32; + MCHBAR32_AND_OR(C0DQSRyTX1(rank), ~((1 << (dqs + 9)) | (1 << dqs)), reg32); reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs * 2) + 16); MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), @@ -942,9 +940,7 @@ static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk) reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9); reg32 |= ((u32) pll->dbsel[f][clk]) << dq; - /* FIXME: Somehow, touching this changes the binary... */ - MCHBAR32(C0DQRyTX1(rank)) = (MCHBAR32(0x5a4 + rank * 4) - & ~((1 << (dq + 9)) | (1 << dq))) | reg32; + MCHBAR32_AND_OR(C0DQRyTX1(rank), ~((1 << (dq + 9)) | (1 << dq)), reg32); reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32); -- cgit v1.2.3