From 10575190746b299abfd0b24d4a42f4c47d2f7504 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 2 Sep 2020 19:24:59 +0200 Subject: nb/intel/ironlake: Use an enum for `gpu_panel_port_select` The PRM does not describe the relevant bits, but Linux's i915 driver handles these bits the same way for both Ironlake and Sandy Bridge. Change-Id: Ice7412e335752bd7e297ad50f685effcefbd41d2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45036 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/ironlake/chip.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h index c437b724a4..b2976bced5 100644 --- a/src/northbridge/intel/ironlake/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -17,7 +17,13 @@ struct northbridge_intel_ironlake_config { u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ + enum { + PANEL_PORT_LVDS = 0, + PANEL_PORT_DP_A = 1, /* Also known as eDP */ + PANEL_PORT_DP_C = 2, + PANEL_PORT_DP_D = 3, + } gpu_panel_port_select; + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ -- cgit v1.2.3