From 065857ee7fd61b05025d7a803e82f2b9b53cbc9a Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Sat, 2 Mar 2019 18:00:29 +0200
Subject: arch/io.h: Drop unnecessary include
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/e7505/memmap.c             | 1 -
 src/northbridge/intel/e7505/northbridge.c        | 1 -
 src/northbridge/intel/fsp_rangeley/acpi.c        | 1 -
 src/northbridge/intel/fsp_rangeley/northbridge.c | 1 -
 src/northbridge/intel/fsp_rangeley/port_access.c | 1 -
 src/northbridge/intel/fsp_rangeley/raminit.c     | 1 -
 src/northbridge/intel/gm45/bootblock.c           | 1 -
 src/northbridge/intel/gm45/early_init.c          | 1 -
 src/northbridge/intel/gm45/igd.c                 | 1 -
 src/northbridge/intel/gm45/iommu.c               | 1 -
 src/northbridge/intel/gm45/northbridge.c         | 1 -
 src/northbridge/intel/gm45/pcie.c                | 1 -
 src/northbridge/intel/gm45/pm.c                  | 1 -
 src/northbridge/intel/gm45/ram_calc.c            | 1 -
 src/northbridge/intel/gm45/stage_cache.c         | 1 -
 src/northbridge/intel/gm45/thermal.c             | 1 -
 src/northbridge/intel/haswell/bootblock.c        | 1 -
 src/northbridge/intel/haswell/finalize.c         | 1 -
 src/northbridge/intel/haswell/northbridge.c      | 1 -
 src/northbridge/intel/haswell/ram_calc.c         | 1 -
 src/northbridge/intel/haswell/report_platform.c  | 1 -
 src/northbridge/intel/i440bx/debug.c             | 1 -
 src/northbridge/intel/i440bx/northbridge.c       | 1 -
 src/northbridge/intel/i440bx/ram_calc.c          | 1 -
 src/northbridge/intel/i945/bootblock.c           | 1 -
 src/northbridge/intel/i945/debug.c               | 1 -
 src/northbridge/intel/i945/northbridge.c         | 1 -
 src/northbridge/intel/i945/ram_calc.c            | 1 -
 src/northbridge/intel/i945/stage_cache.c         | 1 -
 src/northbridge/intel/nehalem/bootblock.c        | 1 -
 src/northbridge/intel/nehalem/finalize.c         | 1 -
 src/northbridge/intel/nehalem/northbridge.c      | 1 -
 src/northbridge/intel/nehalem/ram_calc.c         | 1 -
 src/northbridge/intel/pineview/bootblock.c       | 1 -
 src/northbridge/intel/pineview/northbridge.c     | 1 -
 src/northbridge/intel/pineview/ram_calc.c        | 1 -
 src/northbridge/intel/pineview/stage_cache.c     | 1 -
 src/northbridge/intel/sandybridge/bootblock.c    | 1 -
 src/northbridge/intel/sandybridge/finalize.c     | 1 -
 src/northbridge/intel/sandybridge/northbridge.c  | 1 -
 src/northbridge/intel/sandybridge/ram_calc.c     | 1 -
 src/northbridge/intel/sandybridge/raminit_ivy.c  | 1 -
 src/northbridge/intel/x4x/bootblock.c            | 1 -
 src/northbridge/intel/x4x/gma.c                  | 1 -
 src/northbridge/intel/x4x/northbridge.c          | 1 -
 src/northbridge/intel/x4x/ram_calc.c             | 1 -
 src/northbridge/intel/x4x/raminit_tables.c       | 1 -
 src/northbridge/intel/x4x/stage_cache.c          | 1 -
 48 files changed, 48 deletions(-)

(limited to 'src/northbridge/intel')

diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index afe11bbe01..f7a08bc28d 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -14,7 +14,6 @@
 // Use simple device model for this file even in ramstage
 #define __SIMPLE_DEVICE__
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cbmem.h>
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 0032356697..8c31f7ee83 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -12,7 +12,6 @@
  */
 
 #include <console/console.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c
index 44ec0855c9..901843d0e1 100644
--- a/src/northbridge/intel/fsp_rangeley/acpi.c
+++ b/src/northbridge/intel/fsp_rangeley/acpi.c
@@ -18,7 +18,6 @@
 
 #include <types.h>
 #include <string.h>
-#include <arch/io.h>
 #include <arch/acpi.h>
 #include <device/device.h>
 #include <device/pci.h>
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c
index ca439a0d9a..cd900be438 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.c
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c
@@ -17,7 +17,6 @@
 
 #include <console/console.h>
 #include <arch/acpi.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 #include <delay.h>
diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c
index c93d3bd029..75d1bb2b05 100644
--- a/src/northbridge/intel/fsp_rangeley/port_access.c
+++ b/src/northbridge/intel/fsp_rangeley/port_access.c
@@ -17,7 +17,6 @@
 #define __SIMPLE_DEVICE__
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c
index 675a6f438e..32941357cf 100644
--- a/src/northbridge/intel/fsp_rangeley/raminit.c
+++ b/src/northbridge/intel/fsp_rangeley/raminit.c
@@ -15,7 +15,6 @@
  */
 
 #include <string.h>
-#include <arch/io.h>
 #include <cbmem.h>
 #include <device/pci_def.h>
 #include "northbridge.h"
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index 5b1c301cfd..c076c5506b 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 /* Just re-define these instead of including gm45.h. It blows up romcc. */
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index 723a43f6bf..539d62c408 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -14,7 +14,6 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include "gm45.h"
 
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index b0e2ba9916..b1ce1bef90 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -16,7 +16,6 @@
 
 #include <stdint.h>
 #include <stddef.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 642c8776ef..93e631638e 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -17,7 +17,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <arch/acpi.h>
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index fddb1fe339..eda5e92225 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -15,7 +15,6 @@
 
 #include <cbmem.h>
 #include <console/console.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 1a6e3de1da..c470b8147c 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -17,7 +17,6 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c
index 9390fc7b30..a447a23093 100644
--- a/src/northbridge/intel/gm45/pm.c
+++ b/src/northbridge/intel/gm45/pm.c
@@ -17,7 +17,6 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
-#include <arch/io.h>
 #include <device/pci_def.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/speedstep.h>
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index c1ef30e684..c72055fb3a 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -19,7 +19,6 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/gm45/stage_cache.c b/src/northbridge/intel/gm45/stage_cache.c
index ed3b9d4c4d..cbe4556bab 100644
--- a/src/northbridge/intel/gm45/stage_cache.c
+++ b/src/northbridge/intel/gm45/stage_cache.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <cbmem.h>
 #include <device/pci.h>
 #include <stage_cache.h>
diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c
index 2869a48fd1..3ed75b30af 100644
--- a/src/northbridge/intel/gm45/thermal.c
+++ b/src/northbridge/intel/gm45/thermal.c
@@ -17,7 +17,6 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
-#include <arch/io.h>
 #include <device/pci_def.h>
 #include <spd.h>
 #include "delay.h"
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index d7f4e6e9e9..e503e01fa1 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 /* Just re-define this instead of including haswell.h. It blows up romcc. */
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c
index 5f42518891..1777006b63 100644
--- a/src/northbridge/intel/haswell/finalize.c
+++ b/src/northbridge/intel/haswell/finalize.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <stdlib.h>
 #include <device/pci_ops.h>
 #include "haswell.h"
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 106d9a1f09..ac0b84f1d0 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -17,7 +17,6 @@
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <arch/acpi.h>
-#include <arch/io.h>
 #include <stdint.h>
 #include <delay.h>
 #include <cpu/intel/haswell/haswell.h>
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c
index 24fbb64b97..bdf54d2435 100644
--- a/src/northbridge/intel/haswell/ram_calc.c
+++ b/src/northbridge/intel/haswell/ram_calc.c
@@ -16,7 +16,6 @@
 // Use simple device model for this file even in ramstage
 #define __SIMPLE_DEVICE__
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include "haswell.h"
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 376e63f7d5..df3204753b 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -17,7 +17,6 @@
 #include <arch/cpu.h>
 #include <string.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
 #include "haswell.h"
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index b4d92b0d51..9518618825 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -12,7 +12,6 @@
  */
 
 #include <console/console.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <spd.h>
 #include "raminit.h"
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index ae897662c0..2e4c3a15d3 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -12,7 +12,6 @@
  */
 
 #include <console/console.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c
index 3207688b4d..09a3b03272 100644
--- a/src/northbridge/intel/i440bx/ram_calc.c
+++ b/src/northbridge/intel/i440bx/ram_calc.c
@@ -15,7 +15,6 @@
 
 #define __SIMPLE_DEVICE__
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 1c00e8bebf..604088b1f3 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 /* Just re-define this instead of including i945.h. It blows up romcc. */
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index 370131fb51..2acbc57f3c 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -15,7 +15,6 @@
  */
 
 #include <spd.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 1dff3d14dd..ce7d292a27 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -15,7 +15,6 @@
 
 #include <cbmem.h>
 #include <console/console.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index c797d42f09..124a6a8317 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -16,7 +16,6 @@
 // Use simple device model for this file even in ramstage
 #define __SIMPLE_DEVICE__
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cbmem.h>
diff --git a/src/northbridge/intel/i945/stage_cache.c b/src/northbridge/intel/i945/stage_cache.c
index 26d4e7e5a6..b659796ea8 100644
--- a/src/northbridge/intel/i945/stage_cache.c
+++ b/src/northbridge/intel/i945/stage_cache.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <cbmem.h>
 #include <device/pci.h>
 #include <stage_cache.h>
diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c
index c37aa3a61d..47e9032202 100644
--- a/src/northbridge/intel/nehalem/bootblock.c
+++ b/src/northbridge/intel/nehalem/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 static void bootblock_northbridge_init(void)
diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c
index 7313840606..97f6011ba4 100644
--- a/src/northbridge/intel/nehalem/finalize.c
+++ b/src/northbridge/intel/nehalem/finalize.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <stdlib.h>
 #include <device/pci_ops.h>
 #include "nehalem.h"
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 43ec6ed6bd..6906714457 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -17,7 +17,6 @@
 
 #include <console/console.h>
 #include <arch/acpi.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 #include <delay.h>
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index 3df6f8153f..163f21ce3c 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -17,7 +17,6 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/cpu.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
index f3eab492f5..bd76fb933c 100644
--- a/src/northbridge/intel/pineview/bootblock.c
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #define PCIEXBAR 0x60
 #define MMCONF_256_BUSSES 16
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 94aed89fc2..5ddcd73cea 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -16,7 +16,6 @@
 
 #include <cbmem.h>
 #include <console/console.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index cf9db988e1..a789956ea3 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -16,7 +16,6 @@
 
 #define __SIMPLE_DEVICE__
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci_def.h>
diff --git a/src/northbridge/intel/pineview/stage_cache.c b/src/northbridge/intel/pineview/stage_cache.c
index 3e2f882827..6f949e69bd 100644
--- a/src/northbridge/intel/pineview/stage_cache.c
+++ b/src/northbridge/intel/pineview/stage_cache.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <cbmem.h>
 #include <device/pci.h>
 #include <stage_cache.h>
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index c35a49a51b..15e2de1bcc 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 /* Just re-define this instead of including sandybridge.h. It blows up romcc. */
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c
index 3fb0aa6dee..7051b240ed 100644
--- a/src/northbridge/intel/sandybridge/finalize.c
+++ b/src/northbridge/intel/sandybridge/finalize.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <stdlib.h>
 #include <device/pci_ops.h>
 #include "sandybridge.h"
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 4d00d738cd..ab0554c7df 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -16,7 +16,6 @@
 
 #include <console/console.h>
 #include <arch/acpi.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 #include <delay.h>
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
index 0e5127de94..5cda8a33fe 100644
--- a/src/northbridge/intel/sandybridge/ram_calc.c
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -16,7 +16,6 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/cpu.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c
index 20f30389d8..5c1a58a14d 100644
--- a/src/northbridge/intel/sandybridge/raminit_ivy.c
+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c
@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <console/usb.h>
 #include <delay.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include "raminit_native.h"
 #include "raminit_common.h"
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index b470e955e1..1dfdf19ea4 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include "iomap.h"
 #include "x4x.h"
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index 4c27634955..7e91cc5f5d 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -15,7 +15,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/device.h>
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index c168e38f51..ba51430b20 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -16,7 +16,6 @@
 
 #include <cbmem.h>
 #include <console/console.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index ff3c31b4f5..8f9d739aea 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -21,7 +21,6 @@
 #include <commonlib/helpers.h>
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c
index ebd1562bde..b2b36ca7c8 100644
--- a/src/northbridge/intel/x4x/raminit_tables.c
+++ b/src/northbridge/intel/x4x/raminit_tables.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <stdint.h>
 #include "x4x.h"
 
diff --git a/src/northbridge/intel/x4x/stage_cache.c b/src/northbridge/intel/x4x/stage_cache.c
index ff752e5d11..8862c61db0 100644
--- a/src/northbridge/intel/x4x/stage_cache.c
+++ b/src/northbridge/intel/x4x/stage_cache.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <cbmem.h>
 #include <device/pci.h>
 #include <stage_cache.h>
-- 
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