From bccd2b6c492ee597d6cfebc4b6ec21ebef7252c6 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 2 Aug 2019 06:12:03 +0300 Subject: intel/i945,gm45,pineview,x4x: Fix stage cache location MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The cache is at the end of TSEG. As SMM_RESERVED_SIZE was half of TSEG size, offseting from the start gave same position. Change-Id: I2d5df90b40ff7cd9fde3cbe3cc5090aac74825f7 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34671 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/x4x/ram_calc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src/northbridge/intel/x4x') diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 54295a9cee..dda838760d 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -137,13 +137,12 @@ void *cbmem_top(void) void stage_cache_external_region(void **base, size_t *size) { - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + /* The stage cache lives at the end of the TSEG region. * The top of RAM is defined to be the TSEG base address. */ *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); } /* platform_enter_postcar() determines the stack to use after -- cgit v1.2.3