From 24798a1544a5fa46baca2f7d207fdfbf60517c31 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 13 Aug 2017 16:02:09 +0200 Subject: nb/intel/x4x: Fix booting with FSB800 DDR667 combination A small typo in the dll setting code prevented this combination from booting. TESTED on ga-g41m-es2l with 800MHz FSB CPU and 667MHz ddr2 Change-Id: Ib013471773c20336ba0902b7f328bfb6ef970747 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/20981 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph --- src/northbridge/intel/x4x/raminit_ddr2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel/x4x') diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 9c13fc1995..02c7fee475 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -927,7 +927,7 @@ static void dll_ddr2(struct sysinfo *s) if ((s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) && (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { - i = MCHBAR8(0x180) & 0xf; + i = MCHBAR8(0x1c8) & 0xf; i = (i + 10) % 14; MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; -- cgit v1.2.3