From e951e8ec7f8a5a9d7b9b681526c3b16b67be15d4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 15 Jun 2019 11:03:00 +0200 Subject: nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps} Change-Id: I0442cc5bc54efd7e2c4e5496182c8df85acbcf91 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33491 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/x4x/raminit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/x4x/raminit.c') diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index bd6536ab6f..8013af9d51 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -461,9 +461,9 @@ static void print_selected_timings(struct sysinfo *s) { printk(BIOS_DEBUG, "Selected timings:\n"); printk(BIOS_DEBUG, "\tFSB: %dMHz\n", - fsb2mhz(s->selected_timings.fsb_clk)); + fsb_to_mhz(s->selected_timings.fsb_clk)); printk(BIOS_DEBUG, "\tDDR: %dMHz\n", - ddr2mhz(s->selected_timings.mem_clk)); + ddr_to_mhz(s->selected_timings.mem_clk)); printk(BIOS_DEBUG, "\tCAS: %d\n", s->selected_timings.CAS); printk(BIOS_DEBUG, "\ttRAS: %d\n", s->selected_timings.tRAS); -- cgit v1.2.3