From a4ffe9dda0eb50eb698fef303f426408338fa0ff Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Mon, 27 Jun 2016 13:24:11 +0300
Subject: intel post-car: Separate files for setup_stack_and_mtrrs()
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Have a common romstage.c file to prepare CAR stack guards.

MTRR setup around cbmem_top() is somewhat northbridge specific,
place stubs under northbridge for platrform that will move
to RELOCATABLE_RAMSTAGE.

Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15762
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/northbridge/intel/x4x/ram_calc.c | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/northbridge/intel/x4x/ram_calc.c')

diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 5a6a7675f1..09eec47e72 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -23,6 +23,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
+#include <cpu/intel/romstage.h>
 #include <northbridge/intel/x4x/x4x.h>
 
 /** Decodes used Graphics Mode Select (GMS) to kilobytes. */
@@ -93,3 +94,8 @@ void *cbmem_top(void)
 	u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG);
 	return (void*)(ramtop);
 }
+
+void *setup_stack_and_mtrrs(void)
+{
+	return (void*)CONFIG_RAMTOP;
+}
-- 
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