From 293445ae1f93d38b86b1c1a3c9ee40ec96a36fac Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 27 Feb 2017 21:45:07 +0100 Subject: nb/intel/x4x: Add support for second PEG slot Is only present on the P45 subtype of chipset. Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/18516 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/x4x/northbridge.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/x4x/northbridge.c') diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index c91e7c8b60..6ba45fee0b 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -196,8 +196,12 @@ static void x4x_init(void *const chip_info) struct device *const d0f0 = dev_find_slot(0, 0); /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { + for (dev = 6; dev > 0; --dev) { switch (dev) { + case 6: /* PEG1: only on P45 */ + fn = 0; + bit_base = 13; + break; case 3: /* ME */ fn = 3; bit_base = 6; @@ -206,10 +210,13 @@ static void x4x_init(void *const chip_info) fn = 1; bit_base = 3; break; - case 1: /* PEG */ + case 1: /* PEG0 */ fn = 0; bit_base = 1; break; + case 4: /* Nothing to do */ + case 5: + continue; } for (; fn >= 0; --fn) { const struct device *const d = -- cgit v1.2.3