From d1c590a66654bdb6be6da85c539c9567be6234a0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 3 Aug 2020 16:01:39 +0200 Subject: nb/intel/x4x: Define and use `HOST_BRIDGE` macro Other Intel northbridges do this. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change Change-Id: I50785b7bf3e3cc0eade7fda4b4b2e2bb71a54c31 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/44143 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/x4x/memmap.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/northbridge/intel/x4x/memmap.c') diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 8a69ba80a8..db0ab9c9fb 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -72,7 +72,7 @@ int decode_pcie_bar(u32 *const base, u32 *const len) {0, 0}, }; - const u32 pciexbar_reg = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO); + const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO); if (!(pciexbar_reg & 1)) { printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); @@ -95,13 +95,13 @@ int decode_pcie_bar(u32 *const base, u32 *const len) static size_t northbridge_get_tseg_size(void) { - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); + const u8 esmramc = pci_read_config8(HOST_BRIDGE, D0F0_ESMRAMC); return decode_tseg_size(esmramc); } static uintptr_t northbridge_get_tseg_base(void) { - return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); + return pci_read_config32(HOST_BRIDGE, D0F0_TSEG); } -- cgit v1.2.3