From aa990e928910e35edb115095898c4668becdf1d8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 20:08:12 +0100 Subject: sb/intel/i82801jx: Move early sb init to a common place Setting southbridge GPIO is now done after console init, which should be fine. This code is partially copied from i82801ix. Change-Id: I51dd30de4a82898b0f1d8c4308e8de4a00d1b7aa Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36756 Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/x4x/early_init.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) (limited to 'src/northbridge/intel/x4x/early_init.c') diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index a58f2ba6e9..d48b8f0263 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -42,8 +42,10 @@ void x4x_early_init(void) pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); /* Setup PMBASE */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); + if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); + } /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR); @@ -57,12 +59,14 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33); - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */ - outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */ - outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */ - printk(BIOS_DEBUG, " done.\n"); + if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */ + outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */ + outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */ + printk(BIOS_DEBUG, " done.\n"); + } if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { /* Enable internal GFX */ -- cgit v1.2.3