From 95c48cbbb5b679ddbc2bd115becc04454e4adffd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 4 Nov 2017 08:07:06 +0100 Subject: nb/intel/x4x: Implement both read and write training This training find the optimal write DQ delay and read DQS delay settings. It does so on all lanes at the same time, like vendor (training each lane individually has poor results). The results are stored in the sysinfo struct and restored on next boots and S3 resume. This potentially increases stability as optimal settings are chosen and is more necessary for DDR3 raminit where the write DQS delays are leveled/variable due to the flyby topology. TESTED on Intel DG43GT with (2G + 1G) on each channel, see that the results are quite close to the safe original ones (that previous worked fine) and tested with memtest86+. Change-Id: Iacdc63b91b4705d1a80437314bfe55385ea5b6c1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/22329 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/x4x/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/northbridge/intel/x4x/Makefile.inc') diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index fb9dc1591b..29ece07526 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += raminit_ddr2.c romstage-y += ram_calc.c romstage-y += rcven.c romstage-y += raminit_tables.c +romstage-y += dq_dqs.c ramstage-y += acpi.c ramstage-y += ram_calc.c -- cgit v1.2.3