From 405721d45c8f7cd58c2466e43df8c2aee6f8e714 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Sat, 18 Dec 2010 13:22:37 +0000 Subject: Fix a few whitespace and coding style issues. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/intel/sch/acpi.c | 32 ++-- src/northbridge/intel/sch/early_init.c | 162 +++++++++++---------- src/northbridge/intel/sch/gma.c | 10 +- src/northbridge/intel/sch/northbridge.c | 197 ++++++++++++------------- src/northbridge/intel/sch/nvs.h | 169 +++++++++++----------- src/northbridge/intel/sch/port_access.c | 26 ++-- src/northbridge/intel/sch/raminit.c | 249 +++++++++++++++++++------------- src/northbridge/intel/sch/sch.h | 6 +- 8 files changed, 452 insertions(+), 399 deletions(-) (limited to 'src/northbridge/intel/sch') diff --git a/src/northbridge/intel/sch/acpi.c b/src/northbridge/intel/sch/acpi.c index dbdaf2f7d9..6dd495ffbc 100644 --- a/src/northbridge/intel/sch/acpi.c +++ b/src/northbridge/intel/sch/acpi.c @@ -5,8 +5,7 @@ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -15,8 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include @@ -39,36 +37,38 @@ unsigned long acpi_fill_mcfg(unsigned long current) if (!dev) return current; - pciexbar_reg=pci_read_config32(dev, 0x48); + pciexbar_reg = pci_read_config32(dev, 0x48); - // MMCFG not supported or not enabled. + /* MMCFG not supported or not enabled. */ if (!(pciexbar_reg & (1 << 0))) return current; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + case 0: /* 256MB */ + pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28)); max_buses = 256; break; - case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + case 1: /* 128M */ + pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27)); max_buses = 128; break; - case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + case 2: /* 64M */ + pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27) | (1 << 26)); max_buses = 64; break; - default: // RSVD + default: /* RSVD */ return current; } if (!pciexbar) return current; + #if CONFIG_GENERATE_ACPI_TABLES current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); + pciexbar, 0x0, 0x0, max_buses - 1); #endif return current; } - - diff --git a/src/northbridge/intel/sch/early_init.c b/src/northbridge/intel/sch/early_init.c index 6ec0169f31..b4d8eab815 100644 --- a/src/northbridge/intel/sch/early_init.c +++ b/src/northbridge/intel/sch/early_init.c @@ -18,120 +18,120 @@ */ #include "sch.h" -#include "southbridge/intel/sch/sch.h" +#include #if 0 -static void sch_set_mtrr (void) +static void sch_set_mtrr(void) { msr_t msr; printk(BIOS_DEBUG, "1"); msr.hi = 0x06060606; msr.lo = 0x06060606; - wrmsr (0x250, msr); + wrmsr(0x250, msr); printk(BIOS_DEBUG, "2"); msr.hi = 0x06060606; msr.lo = 0x06060606; - wrmsr (0x258, msr); + wrmsr(0x258, msr); printk(BIOS_DEBUG, "3"); msr.hi = 0x0; msr.lo = 0x0; - wrmsr (0x259, msr); + wrmsr(0x259, msr); printk(BIOS_DEBUG, "4"); msr.hi = 0x04040404; msr.lo = 0x04040404; - wrmsr (0x268, msr); + wrmsr(0x268, msr); printk(BIOS_DEBUG, "5"); msr.hi = 0x04040404; msr.lo = 0x04040404; - wrmsr (0x269, msr); + wrmsr(0x269, msr); printk(BIOS_DEBUG, "6"); msr.hi = 0x04040404; msr.lo = 0x04040404; - wrmsr (0x26A, msr); + wrmsr(0x26A, msr); printk(BIOS_DEBUG, "7"); msr.hi = 0x04040404; msr.lo = 0x04040404; - wrmsr (0x26B, msr); + wrmsr(0x26B, msr); printk(BIOS_DEBUG, "8"); msr.hi = 0x04040404; msr.lo = 0x04040404; - wrmsr (0x26C, msr); + wrmsr(0x26C, msr); printk(BIOS_DEBUG, "9"); msr.hi = 0x05050505; msr.lo = 0x05050505; - wrmsr (0x26D, msr); + wrmsr(0x26D, msr); printk(BIOS_DEBUG, "10"); msr.hi = 0x05050505; msr.lo = 0x05050505; - wrmsr (0x26E, msr); + wrmsr(0x26E, msr); printk(BIOS_DEBUG, "11"); msr.hi = 0x05050505; msr.lo = 0x05050505; - wrmsr (0x26f, msr); + wrmsr(0x26f, msr); printk(BIOS_DEBUG, "12"); msr.hi = 0x0; msr.lo = 0x6; - wrmsr (0x202, msr); + wrmsr(0x202, msr); printk(BIOS_DEBUG, "13"); msr.hi = 0x0; msr.lo = 0xC0000800; - wrmsr (0x203, msr); + wrmsr(0x203, msr); printk(BIOS_DEBUG, "14"); msr.hi = 0x0; msr.lo = 0x3FAF0000; - wrmsr (0x204, msr); + wrmsr(0x204, msr); printk(BIOS_DEBUG, "15"); msr.hi = 0x0; msr.lo = 0xFFFF0800; - wrmsr (0x205, msr); + wrmsr(0x205, msr); printk(BIOS_DEBUG, "16"); msr.hi = 0x0; msr.lo = 0x3FB00000; - wrmsr (0x206, msr); + wrmsr(0x206, msr); printk(BIOS_DEBUG, "16"); msr.hi = 0x0; msr.lo = 0xFFF00800; - wrmsr (0x207, msr); + wrmsr(0x207, msr); printk(BIOS_DEBUG, "17"); msr.hi = 0x0; msr.lo = 0x3FC00000; - wrmsr (0x208, msr); + wrmsr(0x208, msr); printk(BIOS_DEBUG, "18"); msr.hi = 0x0; msr.lo = 0xFFC00800; - wrmsr (0x209, msr); + wrmsr(0x209, msr); printk(BIOS_DEBUG, "19"); msr.hi = 0x0; msr.lo = 0x0; - wrmsr (0x20A, msr); + wrmsr(0x20A, msr); printk(BIOS_DEBUG, "20"); msr.hi = 0x0; msr.lo = 0x0; - wrmsr (0x20B, msr); + wrmsr(0x20B, msr); printk(BIOS_DEBUG, "21"); msr.hi = 0x0; msr.lo = 0x0; - wrmsr (0x20a, msr); + wrmsr(0x20a, msr); printk(BIOS_DEBUG, "22"); msr.hi = 0x0; msr.lo = 0x0; - wrmsr (0x20B, msr); + wrmsr(0x20B, msr); printk(BIOS_DEBUG, "23"); msr.hi = 0x0; msr.lo = 0x0; - wrmsr (0x20c, msr); + wrmsr(0x20c, msr); msr.hi = 0x0; msr.lo = 0x0; - wrmsr (0x20d, msr); + wrmsr(0x20d, msr); msr.hi = 0x0; msr.lo = 0x0; - wrmsr (0x20E, msr); + wrmsr(0x20E, msr); msr.hi = 0x0; msr.lo = 0x0; - wrmsr (0x20F, msr); + wrmsr(0x20F, msr); msr.hi = 0x0; msr.lo = 0XC00; - wrmsr (0x2FF, msr); + wrmsr(0x2FF, msr); printk(BIOS_DEBUG, "end"); } #endif @@ -139,71 +139,81 @@ static void sch_set_mtrr (void) static void sch_detect_chipset(void) { u16 reg16; - u8 reg8; + u8 reg8; printk(BIOS_INFO, "\n"); reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), 0x2); - switch (reg16) - { - case 0x8101: - printk(BIOS_INFO, "UL11L/US15L"); - break; - case 0x8100: - printk(BIOS_INFO, "US15W"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)", reg16); /* Others reserved. */ + switch (reg16) { + case 0x8101: + printk(BIOS_INFO, "UL11L/US15L"); + break; + case 0x8100: + printk(BIOS_INFO, "US15W"); + break; + default: + /* Others reserved. */ + printk(BIOS_INFO, "Unknown (%02x)", reg16); } printk(BIOS_INFO, " Chipset\n"); - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x8); - switch (reg8) - { - case 3: - printk(BIOS_INFO, "Qual. Sample ES1, Stepping B1"); - break; - case 4: - printk(BIOS_INFO, "Qual. Sample ES2, Stepping C0"); - break; - case 5: - printk(BIOS_INFO, "Qual. Sample ES2-Prime, Stepping D0"); - break; - case 6: - printk(BIOS_INFO, "Qual. Sample QS, Stepping D1"); - break; - - default: - printk(BIOS_INFO, "Unknown (%02x)", reg8); /* Others reserved. */ + switch (reg8) { + case 3: + printk(BIOS_INFO, "Qual. Sample ES1, Stepping B1"); + break; + case 4: + printk(BIOS_INFO, "Qual. Sample ES2, Stepping C0"); + break; + case 5: + printk(BIOS_INFO, "Qual. Sample ES2-Prime, Stepping D0"); + break; + case 6: + printk(BIOS_INFO, "Qual. Sample QS, Stepping D1"); + break; + default: + /* Others reserved. */ + printk(BIOS_INFO, "Unknown (%02x)", reg8); } - } static void sch_setup_non_standard_bars(void) { printk(BIOS_DEBUG, "Setting up ACPI PM1 block "); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x48, (0x80000000 |DEFAULT_PMBASE)); /*Address 1000 size 16B*/ + /* Address 0x1000 size 16B */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x48, + (0x80000000 | DEFAULT_PMBASE)); + printk(BIOS_DEBUG, "Setting up ACPI P block "); - sch_port_access_write(4,0x70,4,0x80001010);/*Address 1010 size 16B*/ - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x40, 0x80001040); /*SM Bus Address 1040 size 64B*/ - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x44, 0x80001080); /*GPIO Address 1080 size 64B*/ - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x4C, 0x800010C0); /*GPE0 Address 10C0 size 64B*/ - sch_port_access_write(2,4,4,0x3F703F76); /* FIXME: SMM Control */ - pci_write_config32(PCI_DEV(0, 0x02, 0), 0x5C, 0x3F800000); /*Base of Stolen memory Address 1080 size 64B*/ - - sch_port_access_write(0,0,4, DEFAULT_PCIEXBAR | 1); // pre-b1 - sch_port_access_write(2,9,4, DEFAULT_PCIEXBAR | 1); // b1+ - - /*RCBA*/ - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0, (DEFAULT_RCBABASE| 1 )); - printk(BIOS_DEBUG, " done.\n"); + /* Address 0x1010 size 16B */ + sch_port_access_write(4, 0x70, 4, 0x80001010); + + /* SMBus address 0x1040 size 64B */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x40, 0x80001040); + + /* GPIO address 0x1080 size 64B */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x44, 0x80001080); + /* GPE0 address 0x10C0 size 64B */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x4C, 0x800010C0); + + sch_port_access_write(2, 4, 4, 0x3F703F76); /* FIXME: SMM Control */ + + /* Base of Stolen Memory Address 0x1080 size 64B */ + pci_write_config32(PCI_DEV(0, 0x02, 0), 0x5C, 0x3F800000); + + sch_port_access_write(0, 0, 4, DEFAULT_PCIEXBAR | 1); /* pre-b1 */ + sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */ + + /* RCBA */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0, (DEFAULT_RCBABASE | 1)); + + printk(BIOS_DEBUG, " done.\n"); } static void sch_early_initialization(void) { - /* Print some chipset specific information */ + /* Print some chipset specific information. */ sch_detect_chipset(); - /* Setup all non standard BARs */ + /* Setup all non standard BARs. */ sch_setup_non_standard_bars(); } diff --git a/src/northbridge/intel/sch/gma.c b/src/northbridge/intel/sch/gma.c index 28b4624015..b9a69c2abc 100644 --- a/src/northbridge/intel/sch/gma.c +++ b/src/northbridge/intel/sch/gma.c @@ -26,7 +26,7 @@ static void gma_func0_init(struct device *dev) { u32 reg32; - /* IGD needs to be Bus Master */ + /* IGD needs to be bus master. */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); @@ -37,15 +37,15 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); + pci_read_config32(dev, PCI_VENDOR_ID)); } else { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { @@ -58,10 +58,8 @@ static struct device_operations gma_func0_ops = { .ops_pci = &gma_pci_ops, }; - static const struct pci_driver sch_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x8108, }; - diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index bf2870a8aa..ccd0d331f2 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -41,27 +41,30 @@ static int get_pcie_bar(u32 *base, u32 *len) if (!dev) return 0; - // FIXME: determine at runtime + /* FIXME: Determine at runtime. */ #ifdef POULSBO_PRE_B1 - pciexbar_reg = sch_port_access_read(0,0,4); + pciexbar_reg = sch_port_access_read(0, 0, 4); #else - pciexbar_reg = sch_port_access_read(2,9,4); + pciexbar_reg = sch_port_access_read(2, 9, 4); #endif if (!(pciexbar_reg & (1 << 0))) return 0; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + case 0: /* 256MB */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28)); *len = 256 * 1024 * 1024; return 1; - case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + case 1: /* 128M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27)); *len = 128 * 1024 * 1024; return 1; - case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + case 2: /* 64M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27) | (1 << 26)); *len = 64 * 1024 * 1024; return 1; } @@ -70,7 +73,7 @@ static int get_pcie_bar(u32 *base, u32 *len) } /* IDG memory */ -uint64_t uma_memory_base=0, uma_memory_size=0; +u64 uma_memory_base = 0, uma_memory_size = 0; static void add_fixed_resources(struct device *dev, int index) { @@ -86,7 +89,7 @@ static void add_fixed_resources(struct device *dev, int index) if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar\n"); - resource = new_resource(dev, index+1); + resource = new_resource(dev, index + 1); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | @@ -94,55 +97,52 @@ static void add_fixed_resources(struct device *dev, int index) } printk(BIOS_DEBUG, "Adding CMC shadow area\n"); - resource = new_resource(dev, index+1); + resource = new_resource(dev, index + 1); resource->base = (resource_t) CMC_SHADOW; resource->size = (resource_t) (64 * 1024); resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } - #if CONFIG_WRITE_HIGH_TABLES==1 #include #endif static void pci_domain_set_resources(device_t dev) { - uint32_t pci_tolm; - uint8_t reg8; - uint16_t reg16; + u32 pci_tolm; + u8 reg8; + u16 reg16; unsigned long long tomk, tolud; - /* Can we find out how much memory we can use at most - * this way? - */ + + /* Can we find out how much memory we can use at most this way? */ pci_tolm = find_pci_tolm(dev->link_list); printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm); printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n", - pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c)); + pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c)); tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c); - printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud << 24); + printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud << 24); - tomk = tolud << 14; + tomk = tolud << 14; - /* Note: subtract IGD device and TSEG */ + /* Note: subtract IGD device and TSEG. */ reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e); - if (reg8 & 1) - { + if (reg8 & 1) { int tseg_size = 0; printk(BIOS_DEBUG, "TSEG decoded, subtracting "); reg8 >>= 1; reg8 &= 3; switch (reg8) { case 0: - tseg_size = 1024; - break; /* TSEG = 1M */ + tseg_size = 1024; /* TSEG = 1M */ + break; case 1: - tseg_size = 2048; - break; /* TSEG = 2M */ + tseg_size = 2048; /* TSEG = 2M */ + break; case 2: - tseg_size = 8192; - break; /* TSEG = 8M */ + tseg_size = 8192; /* TSEG = 8M */ + break; } printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10); @@ -150,70 +150,69 @@ static void pci_domain_set_resources(device_t dev) } reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); - if (!(reg16 & 2)) - { + if (!(reg16 & 2)) { int uma_size = 0; printk(BIOS_DEBUG, "IGD decoded, subtracting "); reg16 >>= 4; reg16 &= 7; - switch (reg16) - { - case 1: - uma_size = 1024; - break; - case 2: - uma_size = 4096; - break; - case 3: - uma_size = 8192; - break; + switch (reg16) { + case 1: + uma_size = 1024; + break; + case 2: + uma_size = 4096; + break; + case 3: + uma_size = 8192; + break; } printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); tomk -= uma_size; - /* For reserving UMA memory in the memory map */ + /* For reserving UMA memory in the memory map. */ uma_memory_base = tomk * 1024ULL; uma_memory_size = uma_size * 1024ULL; } - /* The following needs to be 2 lines, otherwise the second - * number is always 0 + /* + * The following needs to be 2 lines, otherwise the second + * number is always 0. */ - printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk); - printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10)); + printk(BIOS_INFO, "Available memory: %dK", (u32) tomk); + printk(BIOS_INFO, " (%dM)\n", (u32) (tomk >> 10)); - /* Report the memory regions */ + /* Report the memory regions. */ ram_resource(dev, 3, 0, 640); ram_resource(dev, 4, 768, (tomk - 768)); - if (tomk > 4 * 1024 * 1024) { + if (tomk > 4 * 1024 * 1024) ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); - } add_fixed_resources(dev, 6); assign_resources(dev->link_list); #if CONFIG_WRITE_HIGH_TABLES==1 - /* Leave some space for ACPI, PIRQ and MP tables */ + /* Leave some space for ACPI, PIRQ and MP tables. */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; #endif } - /* TODO We could determine how many PCIe busses we need in - * the bar. For now that number is hardcoded to a max of 64. - * See e7525/northbridge.c for an example. - */ +/* + * TODO: We could determine how many PCIe busses we need in the bar. For now + * that number is hardcoded to a max of 64. + * See e7525/northbridge.c for an example. + */ static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, #if CONFIG_MMCONF_SUPPORT_DEFAULT - .ops_pci_bus = &pci_ops_mmconf, + .ops_pci_bus = &pci_ops_mmconf, #else - .ops_pci_bus = &pci_cf8_conf1, + .ops_pci_bus = &pci_cf8_conf1, #endif }; @@ -223,32 +222,36 @@ static void mc_read_resources(device_t dev) pci_dev_read_resources(dev); - /* So, this is one of the big mysteries in the coreboot resource + /* + * So, this is one of the big mysteries in the coreboot resource * allocator. This resource should make sure that the address space * of the PCIe memory mapped config space bar. But it does not. */ - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ + /* + * We use 0xcf as an unused index for our PCIe bar so that we find + * it again. + */ resource = new_resource(dev, 0xcf); - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - get_pcie_bar((u32*)&resource->base, (u32*)&resource->size); - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + get_pcie_bar((u32 *)&resource->base, (u32 *)&resource->size); + printk(BIOS_DEBUG, + "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", + (unsigned long)(resource->base), + (unsigned long)(resource->base + resource->size)); } static void mc_set_resources(device_t dev) { struct resource *resource; - /* Report the PCIe BAR */ + /* Report the PCIe BAR. */ resource = find_resource(dev, 0xcf); - if (resource) { + if (resource) report_resource_stored(dev, resource, ""); - } - /* And call the normal set_resources */ + /* And call the normal set_resources. */ pci_dev_set_resources(dev); } @@ -256,10 +259,10 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); + pci_read_config32(dev, PCI_VENDOR_ID)); } else { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } } @@ -271,39 +274,39 @@ static void northbridge_init(struct device *dev) switch (pci_read_config32(dev, SKPAD)) { case 0xcafebabe: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; + acpi_slp_type = 0; break; case 0xcafed00d: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; + acpi_slp_type = 3; break; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; + acpi_slp_type = 0; break; } } #endif static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = intel_set_subsystem, }; static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = mc_set_resources, - .enable_resources = pci_dev_enable_resources, + .read_resources = mc_read_resources, + .set_resources = mc_set_resources, + .enable_resources = pci_dev_enable_resources, #if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, + .init = northbridge_init, #endif - .scan_bus = 0, - .ops_pci = &intel_pci_ops, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, }; static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x8100, + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x8100, }; static void cpu_bus_init(device_t dev) @@ -316,16 +319,16 @@ static void cpu_bus_noop(device_t dev) } static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, }; static void enable_dev(device_t dev) { - /* Set the operations if it is a special bus type */ + /* Set the operations if it is a special bus type. */ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { diff --git a/src/northbridge/intel/sch/nvs.h b/src/northbridge/intel/sch/nvs.h index 3f01f2ace9..38883cb2fe 100644 --- a/src/northbridge/intel/sch/nvs.h +++ b/src/northbridge/intel/sch/nvs.h @@ -20,89 +20,88 @@ */ typedef struct { - u16 osys; - u8 smif; - u8 prm0; - u8 prm1; - u8 scif; - u8 prm2; - u8 prm3; - u8 lckf; - u8 prm4; - u8 prm5; - u32 p80d; - u8 lids; - u8 pwrs; - u8 dbgs; - u8 linxs; - u8 rsvd; - u8 actt; - u8 psvt; - u8 tc1v; - u8 tc2v; - u8 tspv; - u8 crtt; - u8 dtse; - u8 dts1; - u8 dts2; - u8 rsvd2; - u8 bnum; - u8 b0sc, b1sc, b2sc; - u8 b0ss, b1ss, b2ss; - u8 rsvd3[3]; - u8 apic; - u8 mpen; - u8 bten; - u8 ppcm; - u8 pcp0; - u8 pcp1; - u8 rsvd4[4]; - u8 natp; - u8 cmap; - u8 cmbp; - u8 lptp; - u8 fdcp; - u8 rfdv; - u8 hotk; - u8 rtcf; - u8 util; - u8 acin; - u8 igds; - u8 tlst; - u8 cadl; - u8 padl; - u16 cste; - u16 pste; - u16 nste; - u16 sste; - u8 ndid; - u32 did1; - u32 did2; - u32 did3; - u32 did4; - u32 did5; - u8 rsvd5[0xb]; - u8 brtl; - u8 odds; - u8 alse; - u8 alaf; - u8 llow; - u8 lhih; - u8 rsvd6; - u8 emae; - u16 emap; - u16 emal; - u8 rsvd7; - u8 mefe; - u8 igps; - u8 rsvd8[2]; - u8 tpmp; - u8 tpme; - u8 rsvd9[8]; - u8 gtf0[7]; - u8 gtf2[7]; - u8 idem; - u8 idet; - u8 dock; + u16 osys; + u8 smif; + u8 prm0; + u8 prm1; + u8 scif; + u8 prm2; + u8 prm3; + u8 lckf; + u8 prm4; + u8 prm5; + u32 p80d; + u8 lids; + u8 pwrs; + u8 dbgs; + u8 linxs; + u8 rsvd; + u8 actt; + u8 psvt; + u8 tc1v; + u8 tc2v; + u8 tspv; + u8 crtt; + u8 dtse; + u8 dts1; + u8 dts2; + u8 rsvd2; + u8 bnum; + u8 b0sc, b1sc, b2sc; + u8 b0ss, b1ss, b2ss; + u8 rsvd3[3]; + u8 apic; + u8 mpen; + u8 bten; + u8 ppcm; + u8 pcp0; + u8 pcp1; + u8 rsvd4[4]; + u8 natp; + u8 cmap; + u8 cmbp; + u8 lptp; + u8 fdcp; + u8 rfdv; + u8 hotk; + u8 rtcf; + u8 util; + u8 acin; + u8 igds; + u8 tlst; + u8 cadl; + u8 padl; + u16 cste; + u16 pste; + u16 nste; + u16 sste; + u8 ndid; + u32 did1; + u32 did2; + u32 did3; + u32 did4; + u32 did5; + u8 rsvd5[0xb]; + u8 brtl; + u8 odds; + u8 alse; + u8 alaf; + u8 llow; + u8 lhih; + u8 rsvd6; + u8 emae; + u16 emap; + u16 emal; + u8 rsvd7; + u8 mefe; + u8 igps; + u8 rsvd8[2]; + u8 tpmp; + u8 tpme; + u8 rsvd9[8]; + u8 gtf0[7]; + u8 gtf2[7]; + u8 idem; + u8 idet; + u8 dock; } global_nvs_t; - diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c index 73e03c8f81..bdd6b175bf 100644 --- a/src/northbridge/intel/sch/port_access.c +++ b/src/northbridge/intel/sch/port_access.c @@ -5,8 +5,7 @@ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -44,32 +43,33 @@ * | Data | * | | * ---------------------------------------------------------------------------- - * */ + #define MSG_OPCODE_READ 0xD0000000 #define MSG_OPCODE_WRITE 0xE0000000 #define MCR 0xD0 #define MDR 0xD4 -int sch_port_access_read(int port,int reg, int bytes) +int sch_port_access_read(int port, int reg, int bytes) { - pci_write_config32(PCI_DEV(0, 0, 0), MCR, (MSG_OPCODE_READ |(port <<16) | (reg << 8) )); + pci_write_config32(PCI_DEV(0, 0, 0), MCR, + (MSG_OPCODE_READ | (port << 16) | (reg << 8))); return pci_read_config32(PCI_DEV(0, 0, 0), MDR); } -void sch_port_access_write(int port,int reg,int bytes,long data) +void sch_port_access_write(int port, int reg, int bytes, long data) { - pci_write_config32(PCI_DEV(0, 0, 0), MDR,data); - pci_write_config32(PCI_DEV(0, 0, 0), MCR, (MSG_OPCODE_WRITE |(port <<16) | (reg << 8) )); + pci_write_config32(PCI_DEV(0, 0, 0), MDR, data); + pci_write_config32(PCI_DEV(0, 0, 0), MCR, + (MSG_OPCODE_WRITE | (port << 16) | (reg << 8))); pci_read_config32(PCI_DEV(0, 0, 0), MDR); } -void sch_port_access_write_ram_cmd(int cmd,int port,int reg,int data) +void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data) { - - pci_write_config32(PCI_DEV(0, 0, 0), MDR,data); - pci_write_config32(PCI_DEV(0, 0, 0), MCR, ((cmd << 24) |(port <<16) | (reg << 8))); + pci_write_config32(PCI_DEV(0, 0, 0), MDR, data); + pci_write_config32(PCI_DEV(0, 0, 0), MCR, + ((cmd << 24) | (port << 16) | (reg << 8))); pci_read_config32(PCI_DEV(0, 0, 0), MDR); } - diff --git a/src/northbridge/intel/sch/raminit.c b/src/northbridge/intel/sch/raminit.c index d2e8af8970..5e49682e51 100644 --- a/src/northbridge/intel/sch/raminit.c +++ b/src/northbridge/intel/sch/raminit.c @@ -5,8 +5,7 @@ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -24,6 +23,7 @@ #include #include "raminit.h" #include "sch.h" + #define DEBUG_RAM_SETUP #define SOFTSTRSP(base, off) *((volatile u8 *)((base) + (off))) @@ -42,17 +42,18 @@ static void detect_fsb(struct sys_info *sysinfo) { u32 reg32; + reg32 = sch_port_access_read(5, 3, 4); - if (reg32 & BIT(3)) { + if (reg32 & BIT(3)) sysinfo->fsb_frequency = 533; - } else { + else sysinfo->fsb_frequency = 400; - } } static u32 detect_softstrap_base(void) { u32 reg32, base_addr; + reg32 = sch_port_access_read(4, 0x71, 2); reg32 &= 0x700; reg32 = reg32 >> 7; @@ -82,12 +83,12 @@ static void detect_softstraps(struct sys_info *sysinfo) sysinfo->ranks = reg8; if (reg8 == 0) { sysinfo->ram_param_source = RAM_PARAM_SOURCE_SPD; - /* FIXME: implement SPD reading */ - die("no support for reading DIMM config from SPD yet!"); + /* FIXME: Implement SPD reading. */ + die("No support for reading DIMM config from SPD yet!"); return; } else { sysinfo->ram_param_source = RAM_PARAM_SOURCE_SOFTSTRAP; - /*Timings from soft strap */ + /* Timings from soft strap */ reg8 = SOFTSTRSP(sbase, 0x87f0); temp = reg8 & 0x30; temp = temp >> 4; @@ -98,7 +99,7 @@ static void detect_softstraps(struct sys_info *sysinfo) temp = reg8 & 0x03; sysinfo->trp = temp; - /*Geometry from Softstrap */ + /* Geometry from Softstrap */ reg8 = SOFTSTRSP(sbase, 0x87f1); temp = reg8 & 0x06; @@ -108,7 +109,7 @@ static void detect_softstraps(struct sys_info *sysinfo) temp = reg8 & 0x01; sysinfo->data_width = temp; - /*Refresh rate default 7.8us */ + /* Refresh rate default 7.8us */ sysinfo->refresh = 3; } } @@ -117,44 +118,55 @@ static void program_sch_dram_data(struct sys_info *sysinfo) { u32 reg32; - /* Program DRP DRAM Rank Population and Interface Register - * as per data in sysinfo SCH port 1 register 0 .. 0XFF + /* + * Program DRP DRAM Rank Population and Interface Register as per data + * in sysinfo SCH port 1 register 0..0xFF. */ - reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); - reg32 &= ~(DRP_FIELDS); /* Clear all DRP fields we'll change */ + reg32 = + sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); + reg32 &= ~(DRP_FIELDS); /* Clear all DRP fields we'll change. */ /* Rank0 Device Width, Density, Enable */ - reg32 |= (sysinfo->data_width) | ((sysinfo->device_density) << 1) | (1 << 3); + reg32 |= sysinfo->data_width | (sysinfo->device_density << 1) | (1 << 3); /* Rank1 Device Width, Density, Enable */ - reg32 |= (sysinfo->data_width << 4) | ((sysinfo->device_density) << 5) | (1 << 7); - sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4, reg32); + reg32 |= (sysinfo->data_width << 4) + | ((sysinfo->device_density) << 5) | (1 << 7); + sch_port_access_write(SCH_MSG_DUNIT_PORT, + SCH_MSG_DUNIT_REG_DRP, 4, reg32); /* - Program DTR DRAM Timing Register as per data in sysinfo SCH port 1 register 1 - tRD_dly = 2 (15:13 = 010b) - 0X3F - */ - reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DTR, 4); - reg32 &= ~(DTR_FIELDS); /* Clear all DTR fields we'll change */ + * Program DTR DRAM Timing Register as per data in sysinfo SCH port 1 + * register 1. + * + * tRD_dly = 2 (15:13 = 010b) + * 0X3F + */ + reg32 = + sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DTR, 4); + reg32 &= ~(DTR_FIELDS); /* Clear all DTR fields we'll change. */ reg32 = (sysinfo->trp); reg32 |= (sysinfo->trcd) << 2; reg32 |= (sysinfo->cl) << 4; reg32 |= 0X4000; /* tRD_dly = 2 (15:13 = 010b) */ - sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DTR, 4, reg32); - + sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DTR, 4, + reg32); - /* DCO DRAM Controller Operation Register as per data in sysinfo SCH port 1 register 2 0XF */ - reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4); - reg32 &= ~(DCO_FIELDS); /*Clear all DTR fields we'll change */ + /* + * DCO DRAM Controller Operation Register as per data in sysinfo + * SCH port 1 register 2 0xF. + */ + reg32 = + sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4); + reg32 &= ~(DCO_FIELDS); /* Clear all DTR fields we'll change. */ - if (sysinfo->fsb_frequency == 533) { + if (sysinfo->fsb_frequency == 533) reg32 |= 1; - } else { + else reg32 &= ~(BIT(0)); - } - reg32 = 0x006911c; // FIXME ? + reg32 = 0x006911c; // FIXME ? - sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4, reg32); + sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4, + reg32); } static void program_dll_config(struct sys_info *sysinfo) @@ -167,119 +179,152 @@ static void program_dll_config(struct sys_info *sysinfo) sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x22, 4, 0x58585858); } sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x23, 4, 0x2222); - if (sysinfo->fsb_frequency == 533) { + if (sysinfo->fsb_frequency == 533) sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x20, 4, 0x993B); - } else { + else sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x20, 4, 0xCC3B); - } } static void do_jedec_init(struct sys_info *sysinfo) { u32 reg32, rank, cmd, temp, num_ranks; + /* Performs JEDEC memory initializattion for all memory rows */ /* Set CKE0/1 low */ - reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); + reg32 = + sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); reg32 |= DRP_CKE_DIS; - sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4, reg32); - reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); + sch_port_access_write(SCH_MSG_DUNIT_PORT, + SCH_MSG_DUNIT_REG_DRP, 4, reg32); + reg32 = + sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); rank = 0; num_ranks = sysinfo->ranks; - do { + do { /* Start clocks */ - reg32 = - sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); - reg32 &= ~(DRP_SCK_DIS); /* Enable all SCK/SCKB by def. */ + reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, + SCH_MSG_DUNIT_REG_DRP, 4); + reg32 &= ~(DRP_SCK_DIS); /* Enable all SCK/SCKB by def. */ sch_port_access_write(1, SCH_MSG_DUNIT_REG_DRP, 4, reg32); - /* Program miscellaneous SCH registers on rank 0 initialization */ - reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); - if (rank == 0) { + /* Program misc. SCH registers on rank 0 initialization. */ + reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, + SCH_MSG_DUNIT_REG_DRP, 4); + if (rank == 0) program_dll_config(sysinfo); - } printk(BIOS_DEBUG, "Setting up RAM \n"); + /* - Wait 200us - reg32 = inb(ACPI_BASE + 8); PM1 Timer - reg32 &=0xFFFFFF; - reg32 +=0x2EE; - do - { - reg32 = inb(ACPI_BASE + 8);PM1 Timer - reg32 &= 0xFFFFFF; - }while (reg32 < 0x2EE); */ - /* Apply NOP */ + * Wait 200us + * reg32 = inb(ACPI_BASE + 8); PM1 Timer + * reg32 &=0xFFFFFF; + * reg32 +=0x2EE; + * do { + * reg32 = inb(ACPI_BASE + 8);PM1 Timer + * reg32 &= 0xFFFFFF; + * } while (reg32 < 0x2EE); + */ + + /* Apply NOP. */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_NOP; - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); - /* Set CKE=high */ - reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); - reg32 &= 0xFFFF9FFF; /* Clear both the CKE static disables */ - sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4, reg32); - /* Wait 400ns (not needed when executing from flash) - Precharge all + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); + /* Set CKE=high. */ + reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, + SCH_MSG_DUNIT_REG_DRP, 4); + reg32 &= 0xFFFF9FFF; /* Clear both the CKE static disables. */ + sch_port_access_write(SCH_MSG_DUNIT_PORT, + SCH_MSG_DUNIT_REG_DRP, 4, reg32); + /* + * Wait 400ns (not needed when executing from flash). + * Precharge all. */ - reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); + reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, + SCH_MSG_DUNIT_REG_DRP, 4); cmd = rank; cmd |= SCH_DRAMINIT_CMD_PALL; - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); - /*EMRS(2); High temp self refresh=disabled, partial array self refresh=full */ + /* + * EMRS(2); High temp self refresh=disabled, + * partial array self refresh=full. + */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_EMRS2; - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); - /*EMRS(3) (no command) */ + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); + + /* EMRS(3) (no command). */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_EMRS3; - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); - /*EMRS(1); Enable DLL (Leave all bits in the command at 0) */ + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); + + /* EMRS(1); Enable DLL (Leave all bits in the command at 0). */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_EMRS1; - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); - /*MRS; Reset DLL (Set memory address bit 8) */ + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); + + /* MRS; Reset DLL (Set memory address bit 8). */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_MRS; cmd |= (SCH_JEDEC_DLLRESET << SCH_DRAMINIT_ADDR_OFFSET); - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); - /*Precharge all */ + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); + + /* Precharge all. */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_PALL; - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); - /*Issue 2 auto-refresh commands */ + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); + + /* Issue 2 auto-refresh commands. */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_AREF; - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); - /*MRS command including tCL, tWR, burst length (always 4) */ + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); + + /* MRS command including tCL, tWR, burst length (always 4). */ cmd = rank; - cmd |= (SCH_DRAMINIT_CMD_MRS + JEDEC_STATIC_PARAM); /*Static param */ + cmd |= (SCH_DRAMINIT_CMD_MRS + JEDEC_STATIC_PARAM); /* Static param */ temp = sysinfo->cl; - temp += TCL_LOW; /*Adjust for the TCL base */ - temp = temp << ((SCH_JEDEC_CL_OFFSET + SCH_DRAMINIT_ADDR_OFFSET)); /*Ready the CAS latency */ + temp += TCL_LOW; /* Adjust for the TCL base. */ + temp = temp << ((SCH_JEDEC_CL_OFFSET + + SCH_DRAMINIT_ADDR_OFFSET)); /* Ready the CAS latency */ cmd |= temp; - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); - /* Wait 200 clocks (max of 1us, so no need to delay) - Issue EMRS(1):OCD default + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); + + /* + * Wait 200 clocks (max of 1us, so no need to delay). + * Issue EMRS(1):OCD default. */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_EMRS1; cmd |= (SCH_JEDEC_OCD_DEFAULT << SCH_DRAMINIT_ADDR_OFFSET); - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); - /*Issue EMRS(1): OCD cal. mode exit. */ + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); + + /* Issue EMRS(1): OCD cal. mode exit. */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_EMRS1; cmd |= (SCH_JEDEC_DQS_DIS << SCH_DRAMINIT_ADDR_OFFSET); - sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd); + sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, + SCH_MSG_DUNIT_PORT, 0, cmd); rank += SCH_DRAMINIT_RANK_MASK; num_ranks--; } while (num_ranks); } /** - * @param boot_mode: 0 = normal, 1 = resume + * @param boot_mode 0 = normal, 1 = resume */ - void sdram_initialize(int boot_mode) { struct sys_info sysinfo; @@ -289,27 +334,27 @@ void sdram_initialize(int boot_mode) memset(&sysinfo, 0, sizeof(sysinfo)); - detect_fsb(&sysinfo); detect_softstraps(&sysinfo); program_sch_dram_data(&sysinfo); /* cold boot */ - if (boot_mode == BOOT_MODE_NORMAL) { + if (boot_mode == BOOT_MODE_NORMAL) do_jedec_init(&sysinfo); - } else { + else program_dll_config(&sysinfo); - } - /* raminit complete */ - reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4); + /* RAM init complete. */ + reg32 = + sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4); reg32 |= DCO_IC; reg32 |= ((sysinfo.refresh) << 2); reg32 = 0x006919c; - sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4, reg32); + sch_port_access_write(SCH_MSG_DUNIT_PORT, + SCH_MSG_DUNIT_REG_DCO, 4, reg32); - /* setting up TOM */ + /* Setting up TOM. */ reg32 = 0x10000000; reg32 = reg32 >> sysinfo.data_width; reg32 = reg32 << sysinfo.device_density; @@ -317,15 +362,13 @@ void sdram_initialize(int boot_mode) reg32 = 0x40000000; sch_port_access_write(2, 8, 4, reg32); - /* resume mode */ - if (boot_mode == BOOT_MODE_RESUME) { + /* Resume mode. */ + if (boot_mode == BOOT_MODE_RESUME) sch_port_access_write_ram_cmd(SCH_OPCODE_WAKEFULLON, SCH_MSG_DUNIT_PORT, 0, 0); - } sch_port_access_write(2, 0, 4, 0x98); sch_port_access_write(2, 3, 4, 0x7); sch_port_access_write(3, 2, 4, 0x408); sch_port_access_write(4, 0x71, 4, 0x600); } - diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h index f4f334c681..3b0214cd33 100644 --- a/src/northbridge/intel/sch/sch.h +++ b/src/northbridge/intel/sch/sch.h @@ -22,9 +22,9 @@ #ifndef __SCH_PULSBO_H__ #define __SCH_PULSBO_H__ 1 -int sch_port_access_read(int port,int reg, int bytes); -void sch_port_access_write(int port,int reg,int bytes,long data); -void sch_port_access_write_ram_cmd(int cmd,int port,int reg,int data); +int sch_port_access_read(int port, int reg, int bytes); +void sch_port_access_write(int port, int reg, int bytes, long data); +void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data); /* Southbridge IO BARs */ /* TODO Make sure these don't get changed by stage2 */ -- cgit v1.2.3