From ffbb3c0b8abea621eb7a1583d630cf06c8cbfbbc Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Wed, 10 Feb 2016 01:36:25 +0100 Subject: Merge sandy/ivybridge romstage flow for MRC and non-MRC. Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa Signed-off-by: Vladimir Serbinenko Reviewed-on: https://review.coreboot.org/13656 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Martin Roth --- src/northbridge/intel/sandybridge/Makefile.inc | 3 +- src/northbridge/intel/sandybridge/raminit.c | 44 +++++++++++++++ src/northbridge/intel/sandybridge/raminit.h | 1 + src/northbridge/intel/sandybridge/raminit_mrc.c | 27 ++++++++++ src/northbridge/intel/sandybridge/raminit_native.h | 8 ++- src/northbridge/intel/sandybridge/romstage.c | 63 +++++++++------------- src/northbridge/intel/sandybridge/sandybridge.h | 8 +++ 7 files changed, 108 insertions(+), 46 deletions(-) (limited to 'src/northbridge/intel/sandybridge') diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 2d68c03d87..90abe4dab6 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -28,11 +28,10 @@ romstage-y += ram_calc.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += raminit_mrc.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += raminit_mrc.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += raminit.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += romstage.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ../../../device/dram/ddr3.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += romstage.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ../../../device/dram/ddr3.c +romstage-y += romstage.c romstage-y += mrccache.c romstage-y += iommu.c romstage-y += early_init.c diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index aae963e239..7490ff7f29 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -24,12 +24,14 @@ #include #include #include +#include #include #include #include "raminit_native.h" #include "sandybridge.h" #include #include +#include /* Management Engine is in the southbridge */ #include "southbridge/intel/bd82x6x/me.h" @@ -37,6 +39,7 @@ #include "southbridge/intel/bd82x6x/smbus.h" #include "arch/cpu.h" #include "cpu/x86/msr.h" +#include /* FIXME: no ECC support. */ /* FIXME: no support for 3-channel chipsets. */ @@ -4034,3 +4037,44 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, halt(); } } + +#define HOST_BRIDGE PCI_DEVFN(0, 0) +#define DEFAULT_TCK TCK_800MHZ + +static unsigned int get_mem_min_tck(void) +{ + const struct device *dev; + const struct northbridge_intel_sandybridge_config *cfg; + + dev = dev_find_slot(0, HOST_BRIDGE); + if (!(dev && dev->chip_info)) + return DEFAULT_TCK; + + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (cfg->max_mem_clock_mhz == 0) + return DEFAULT_TCK; + + if (cfg->max_mem_clock_mhz >= 800) + return TCK_800MHZ; + else if (cfg->max_mem_clock_mhz >= 666) + return TCK_666MHZ; + else if (cfg->max_mem_clock_mhz >= 533) + return TCK_533MHZ; + return TCK_400MHZ; +} + +void perform_raminit(int s3resume) +{ + spd_raw_data spd[4]; + + post_code(0x3a); + + memset (spd, 0, sizeof (spd)); + mainboard_get_spd(spd); + + timestamp_add_now(TS_BEFORE_INITRAM); + + init_dram_ddr3(spd, 1, get_mem_min_tck(), s3resume); +} diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 5bda2ef2b6..4e684ec409 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -27,6 +27,7 @@ struct sys_info { void sdram_initialize(struct pei_data *pei_data); void save_mrc_data(struct pei_data *pei_data); +void mainboard_fill_pei_data(struct pei_data *pei_data); int fixup_sandybridge_errata(void); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a370eccd31..162caf6107 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "raminit.h" #include "pei_data.h" #include "sandybridge.h" @@ -279,3 +280,29 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } + +void perform_raminit(int s3resume) +{ + int cbmem_was_initted; + struct pei_data pei_data; + + /* Prepare USB controller early in S3 resume */ + if (!mainboard_should_reset_usb(s3resume)) + enable_usb_bar(); + + mainboard_fill_pei_data(&pei_data); + + post_code(0x3a); + pei_data.boot_mode = s3resume ? 2 : 0; + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(&pei_data); + cbmem_was_initted = !cbmem_recovery(s3resume); + if (!s3resume) + save_mrc_data(&pei_data); + + if (s3resume && !cbmem_was_initted) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + halt(); + } +} diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index b41aa855aa..8f8d057313 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -13,17 +13,15 @@ * GNU General Public License for more details. */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef RAMINIT_NATIVE_H +#define RAMINIT_NATIVE_H +#include "sandybridge.h" #include /* The order is ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB. */ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int s3resume); void read_spd(spd_raw_data *spd, u8 addr); void mainboard_get_spd(spd_raw_data *spd); -void rcba_config(void); -void pch_enable_lpc(void); -void mainboard_early_init(int s3resume); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 3d05f8e3fa..04db608f83 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -29,43 +29,23 @@ #include #include #include -#include "raminit_native.h" #include #include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/gpio.h" -#define HOST_BRIDGE PCI_DEVFN(0, 0) -#define DEFAULT_TCK TCK_800MHZ - -static unsigned int get_mem_min_tck(void) +static void early_pch_init(void) { - const struct device *dev; - const struct northbridge_intel_sandybridge_config *cfg; - - dev = dev_find_slot(0, HOST_BRIDGE); - if (!(dev && dev->chip_info)) - return DEFAULT_TCK; - - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (cfg->max_mem_clock_mhz == 0) - return DEFAULT_TCK; - - if (cfg->max_mem_clock_mhz >= 800) - return TCK_800MHZ; - else if (cfg->max_mem_clock_mhz >= 666) - return TCK_666MHZ; - else if (cfg->max_mem_clock_mhz >= 533) - return TCK_533MHZ; - else - return TCK_400MHZ; + u8 reg8; + + // reset rtc power status + reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); } void main(unsigned long bist) { int s3resume = 0; - spd_raw_data spd[4]; if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); @@ -86,7 +66,14 @@ void main(unsigned long bist) setup_pch_gpios(&mainboard_gpio_map); - early_usb_init(mainboard_usb_ports); + /* Initialize superio */ + mainboard_config_superio(); + + /* USB is inited in MRC if MRC is used. */ + if (!(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC + || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC)) { + early_usb_init(mainboard_usb_ports); + } /* Initialize console device(s) */ console_init(); @@ -111,27 +98,25 @@ void main(unsigned long bist) post_code(0x39); - post_code(0x3a); - - memset (spd, 0, sizeof (spd)); - mainboard_get_spd(spd); - - timestamp_add_now(TS_BEFORE_INITRAM); - - init_dram_ddr3(spd, 1, get_mem_min_tck(), s3resume); + perform_raminit(s3resume); timestamp_add_now(TS_AFTER_INITRAM); + + post_code(0x3b); + /* Perform some initialization that must run before stage2 */ + early_pch_init(); post_code(0x3c); southbridge_configure_default_intmap(); rcba_config(); + post_code(0x3d); northbridge_romstage_finalize(s3resume); -#if CONFIG_LPC_TPM - init_tpm(s3resume); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(s3resume); + } post_code(0x3f); } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 0a1f20a06f..570e1f7864 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -215,8 +215,16 @@ void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); void report_platform_info(void); + #endif /* !__SMM__ */ +void rcba_config(void); +void pch_enable_lpc(void); +void mainboard_early_init(int s3resume); +void mainboard_config_superio(void); +int mainboard_should_reset_usb(int s3resume); +void perform_raminit(int s3resume); + #if ENV_RAMSTAGE #include -- cgit v1.2.3