From fc5d85cc66046b239fdd45ff422d70146da1030c Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 18 Nov 2016 18:52:04 +0200 Subject: intel sandy/ivy: Change CRC used to detect DIMM replacement MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switch to use CRC of unique identifier section SPD[117..127], remaining area of SPD data is ignored. Change-Id: If4b43183f99f5f911ae6c311b43c29a72b9922e2 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17487 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Reviewed-by: Patrick Rudolph --- src/northbridge/intel/sandybridge/raminit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/sandybridge') diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0842d4bf93..6ae253dbfe 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -355,7 +355,7 @@ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; match &= ctrl->spd_crc[channel][slot] == - spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); } } return match; @@ -415,7 +415,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) /* fill in CRC16 for MRC cache */ ctrl->spd_crc[channel][slot] = - spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { // set dimm invalid -- cgit v1.2.3