From c70eed1e6202c928803f3e7f79161cd247a62b23 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 22 May 2018 02:18:00 +0300 Subject: device: Use pcidev_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/acpi.c | 4 ++-- src/northbridge/intel/sandybridge/gma.c | 4 ++-- .../intel/sandybridge/gma_ivybridge_lvds.c | 2 +- .../intel/sandybridge/gma_sandybridge_lvds.c | 2 +- src/northbridge/intel/sandybridge/iommu.c | 3 +-- src/northbridge/intel/sandybridge/northbridge.c | 28 +++++++++++----------- 6 files changed, 21 insertions(+), 22 deletions(-) (limited to 'src/northbridge/intel/sandybridge') diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 0a31c8570d..c7914a0a45 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -29,7 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses; - struct device *const dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *const dev = pcidev_on_root(0, 0); if (!dev) return current; @@ -68,7 +68,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) static unsigned long acpi_fill_dmar(unsigned long current) { - const struct device *const igfx = dev_find_slot(0, PCI_DEVFN(2, 0)); + const struct device *const igfx = pcidev_on_root(2, 0); if (igfx && igfx->enabled) { const unsigned long tmp = current; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index cd8f7b9e22..150f78aa4f 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -684,7 +684,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor, const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = pcidev_on_root(0x2, 0); if (!dev) { return NULL; } @@ -737,7 +737,7 @@ static const char *gma_acpi_name(const struct device *dev) static void gma_func0_disable(struct device *dev) { u16 reg16; - struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0,0)); + struct device *dev_host = pcidev_on_root(0, 0); reg16 = pci_read_config16(dev_host, GGC); reg16 |= (1 << 1); /* disable VGA decode */ diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 23ecd44835..6371c16188 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -504,7 +504,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info, write32(mmio + 0x0004f05c, 0x00000008); /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + generate_fake_intel_oprom(info, pcidev_on_root(2, 0), "$VBT SNB/IVB-MOBILE"); return 1; diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 5e8c18855f..977cca8c61 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -469,7 +469,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, } /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + generate_fake_intel_oprom(info, pcidev_on_root(2, 0), "$VBT SNB/IVB-MOBILE"); return 1; diff --git a/src/northbridge/intel/sandybridge/iommu.c b/src/northbridge/intel/sandybridge/iommu.c index 08fbe05102..017c73233c 100644 --- a/src/northbridge/intel/sandybridge/iommu.c +++ b/src/northbridge/intel/sandybridge/iommu.c @@ -37,8 +37,7 @@ void sandybridge_init_iommu(void) /* lock policies */ write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); - const struct device *const azalia = - dev_find_slot(0x00, PCI_DEVFN(0x1b, 0)); + const struct device *const azalia = pcidev_on_root(0x1b, 0); if (azalia && azalia->enabled) { write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5ec8292f62..4a8419a32c 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -42,7 +42,7 @@ int bridge_silicon_revision(void) if (bridge_revision_id < 0) { uint8_t stepping = cpuid_eax(1) & 0xf; uint8_t bridge_id = pci_read_config16( - dev_find_slot(0, PCI_DEVFN(0, 0)), + pcidev_on_root(0, 0), PCI_DEVICE_ID) & 0xf0; bridge_revision_id = bridge_id | stepping; } @@ -65,7 +65,7 @@ static int get_pcie_bar(u32 *base) *base = 0; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (!dev) return 0; @@ -151,7 +151,7 @@ static void pci_domain_set_resources(struct device *dev) * 14fe00000 5368MB TOUUD */ - struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *mch = pcidev_on_root(0, 0); /* Top of Upper Usable DRAM, including remap */ touud = pci_read_config32(mch, TOUUD+4); @@ -351,46 +351,46 @@ static void disable_peg(void) struct device *dev; u32 reg; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); reg = pci_read_config32(dev, DEVEN); - dev = dev_find_slot(0, PCI_DEVFN(1, 2)); + dev = pcidev_on_root(1, 2); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling PEG12.\n"); reg &= ~DEVEN_PEG12; } - dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + dev = pcidev_on_root(1, 1); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling PEG11.\n"); reg &= ~DEVEN_PEG11; } - dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + dev = pcidev_on_root(1, 0); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling PEG10.\n"); reg &= ~DEVEN_PEG10; } - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + dev = pcidev_on_root(2, 0); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling IGD.\n"); reg &= ~DEVEN_IGD; } - dev = dev_find_slot(0, PCI_DEVFN(4, 0)); + dev = pcidev_on_root(4, 0); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling Device 4.\n"); reg &= ~DEVEN_D4EN; } - dev = dev_find_slot(0, PCI_DEVFN(6, 0)); + dev = pcidev_on_root(6, 0); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling PEG60.\n"); reg &= ~DEVEN_PEG60; } - dev = dev_find_slot(0, PCI_DEVFN(7, 0)); + dev = pcidev_on_root(7, 0); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling Device 7.\n"); reg &= ~DEVEN_D7EN; } - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); pci_write_config32(dev, DEVEN, reg); if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) { /* Set the PEG clock gating bit. @@ -469,7 +469,7 @@ static u32 northbridge_get_base_reg(struct device *dev, int reg) u32 northbridge_get_tseg_base(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); return northbridge_get_base_reg(dev, TSEG); } @@ -481,7 +481,7 @@ u32 northbridge_get_tseg_size(void) void northbridge_write_smram(u8 smram) { - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram); + pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); } static struct pci_operations intel_pci_ops = { -- cgit v1.2.3