From 68ff33720a234d72e1b7152512198165e2cfc8e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 21 Nov 2021 13:47:25 +0100 Subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initialize the DPR register and check if SCLEAN needs to be run. Allows to reliably boot the platform if ungraceful shutdown occured or the memory controller has been locked by TXT. TEST=Dell OptiPlex 9010 with Intel TXT enabled boots successfully after 4s power button override or power cable unplug when SENTER was executed. Successfully boot QubesOS 4.0 with TBoot v1.8.2 Signed-off-by: Michał Żygowski Change-Id: I4b912f121593fa55c11813262f09be1a1055e950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59523 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/romstage.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'src/northbridge/intel/sandybridge') diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index d6e7ee9025..71b8e12782 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -10,6 +10,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -22,6 +25,21 @@ __weak void mainboard_late_rcba_config(void) { } +static void configure_dpr(void) +{ + union dpr_register dpr = txt_get_chipset_dpr(); + + /* + * Just need to program the size of DPR, enable and lock it. + * The dpr.top will always point to TSEG_BASE (updated by hardware). + * We do it early because it will be needed later to calculate cbmem_top. + */ + dpr.lock = 1; + dpr.epm = 1; + dpr.size = CONFIG_INTEL_TXT_DPR_SIZE; + pci_write_config32(HOST_BRIDGE, DPR, dpr.raw); +} + static void early_pch_reset_pmcon(void) { /* Reset RTC power status */ @@ -60,6 +78,11 @@ void mainboard_romstage_entry(void) post_code(0x39); + if (CONFIG(INTEL_TXT)) { + configure_dpr(); + intel_txt_romstage_init(); + } + perform_raminit(s3resume); post_code(0x3b); -- cgit v1.2.3