From 31402178c56108e752b95c34562b6e3554a2c1d8 Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Sat, 23 Mar 2024 15:10:04 +0100 Subject: tree: Remove blank lines before '}' and after '{' Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/raminit.c | 1 - src/northbridge/intel/sandybridge/raminit_common.c | 6 ------ src/northbridge/intel/sandybridge/raminit_mrc.c | 1 - src/northbridge/intel/sandybridge/raminit_native.c | 1 - 4 files changed, 9 deletions(-) (limited to 'src/northbridge/intel/sandybridge') diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 085292bb22..2b59b9e6af 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -377,7 +377,6 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) /* Before reusing training data, assert that the CPU has not been replaced */ if (ctrl_cached && cpuid != ctrl_cached->cpu) { - /* It is not really worrying on a cold boot, but fatal when resuming from S3 */ printk(s3resume ? BIOS_ALERT : BIOS_NOTICE, "CPUID %x differs from stored CPUID %x, CPU was replaced!\n", diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3f5e290c57..f896541288 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -64,7 +64,6 @@ void dram_find_common_params(ramctr_timing *ctrl) valid_dimms = 0; FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { - const struct dimm_attr_ddr3_st *dimm = &dimms->dimm[channel][slot]; if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) continue; @@ -1138,7 +1137,6 @@ static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, i int lane, i; for (rcven_delta = -25; rcven_delta <= 25; rcven_delta++) { - FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].rcven = upperA[lane] + rcven_delta + QCLK_PI; @@ -1358,7 +1356,6 @@ int receive_enable_calibration(ramctr_timing *ctrl) FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].rcven -= QCLK_PI; upperA[lane] -= QCLK_PI; - } } else if (some_high) { ctrl->timings[channel][slotrank].roundtrip_latency++; @@ -1657,7 +1654,6 @@ static void train_write_flyby(ramctr_timing *ctrl) fill_pattern1(ctrl, channel); } FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { - /* Reset read and write WDB pointers */ mchbar_write32(IOSAV_DATA_CTL_ch(channel), 0x10001); @@ -2501,7 +2497,6 @@ int aggressive_write_training(ramctr_timing *ctrl) upper[channel][slotrank][lane] = MIN(rn.end - ctrl->tx_dq_offset[i], upper[channel][slotrank][lane]); - } } } @@ -2621,7 +2616,6 @@ void channel_scrub(ramctr_timing *ctrl) rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; for (bank = 0; bank < 8; bank++) { for (row = 0; row < rowsize; row += 16) { - u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD); const struct iosav_ssq sequence[] = { /* diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 82e3e82842..cad86ba51e 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -295,7 +295,6 @@ static void devicetree_fill_pei_data(struct pei_data *pei_data) case 800: pei_data->max_ddr3_freq = 1600; break; - } /* diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index fbdc27a7b0..ecae91be08 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -274,7 +274,6 @@ static unsigned int get_mem_min_tck(void) /* If non-zero, it was set in the devicetree */ if (cfg->max_mem_clock_mhz) { - if (cfg->max_mem_clock_mhz >= 1066) return TCK_1066MHZ; -- cgit v1.2.3