From 243aa44b74935cfc969106dbbe2420ee4a2c39b2 Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Wed, 24 Apr 2013 17:31:49 -0500
Subject: boot: remove cbmem_post_handling()

The cbmem_post_handling() function was implemented by 2
chipsets in order to save memory configuration in flash. Convert
both of these chipsets to use the boot state machine callbacks
to perform the saving of the memory configuration.

Change-Id: I697e5c946281b85a71d8533437802d7913135af3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3137
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
---
 src/northbridge/intel/sandybridge/mrccache.c    | 8 +++++++-
 src/northbridge/intel/sandybridge/northbridge.c | 5 -----
 src/northbridge/intel/sandybridge/sandybridge.h | 2 --
 3 files changed, 7 insertions(+), 8 deletions(-)

(limited to 'src/northbridge/intel/sandybridge')

diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index 9c6330ca34..745958abe9 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -19,6 +19,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <bootstate.h>
 #include <console/console.h>
 #include <cbfs.h>
 #include <ip_checksum.h>
@@ -153,7 +154,7 @@ static struct mrc_data_container *find_next_mrc_cache
 	return mrc_cache;
 }
 
-void update_mrc_cache(void)
+static void update_mrc_cache(void *unused)
 {
 	printk(BIOS_DEBUG, "Updating MRC cache data.\n");
 	struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA);
@@ -222,6 +223,11 @@ void update_mrc_cache(void)
 	flash->write(flash, to_flash_offset(cache),
 		     current->mrc_data_size + sizeof(*current), current);
 }
+
+BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = {
+	BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
+	                      update_mrc_cache, NULL),
+};
 #endif
 
 struct mrc_data_container *find_current_mrc_cache(void)
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index b8022b8cea..0a413b4c7b 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -60,11 +60,6 @@ int bridge_silicon_revision(void)
 static const int legacy_hole_base_k = 0xa0000 / 1024;
 static const int legacy_hole_size_k = 384;
 
-void cbmem_post_handling(void)
-{
-	update_mrc_cache();
-}
-
 static int get_pcie_bar(u32 *base, u32 *len)
 {
 	device_t dev;
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index bb1b1a396f..291ea46d8b 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -233,8 +233,6 @@ struct mrc_data_container {
 
 struct mrc_data_container *find_current_mrc_cache(void);
 #if !defined(__PRE_RAM__)
-void update_mrc_cache(void);
-
 #include "gma.h"
 int init_igd_opregion(igd_opregion_t *igd_opregion);
 #endif
-- 
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