From 098240eb4fd4ef59510d5138538f2a2f7cc5dcdc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 22 Mar 2020 12:55:32 +0100 Subject: nb/intel/sandybridge: Use IOSAV_BYTE_SERROR_C_ch macro This changes the binary because the operations get reordered, but it is otherwise equivalent. Change-Id: I362187b2889e6f7a68bf752a23c1279cebf961f2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39758 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/sandybridge/raminit_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/northbridge/intel/sandybridge') diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index a8480a7661..d10b859575 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2626,7 +2626,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr } /* FIXME: This register only exists on Ivy Bridge */ - raw_stats[edge] = MCHBAR32(0x436c + channel * 0x400); + raw_stats[edge] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); } FOR_ALL_LANES { @@ -2797,8 +2797,8 @@ int discover_timC_write(ramctr_timing *ctrl) test_timC_write (ctrl, channel, slotrank); /* FIXME: Another IVB-only register! */ - raw_stats[timC] = - MCHBAR32(0x436c + channel * 0x400); + raw_stats[timC] = MCHBAR32( + IOSAV_BYTE_SERROR_C_ch(channel)); } FOR_ALL_LANES { struct run rn; -- cgit v1.2.3