From dee167ee392be3350996507c22d74e5aef08248a Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 30 Dec 2019 17:30:16 +0100 Subject: nb/intel/sandybridge: add and use more MCHBAR register defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie0a9be0899830a2bf9a994d10c417b0968d1cd47 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/38010 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/raminit_mrc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/northbridge/intel/sandybridge/raminit_mrc.c') diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 84100e7ef6..cab5588ced 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -149,9 +149,9 @@ static void report_memory_config(void) u32 addr_decoder_common, addr_decode_ch[2]; int i; - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); -- cgit v1.2.3