From dabebc3716bac1dbe9445dfb2bbbbb833ee21de1 Mon Sep 17 00:00:00 2001 From: Dan Elkouby Date: Fri, 13 Apr 2018 18:47:10 +0300 Subject: nb/intel/sandybridge: support more XMP timings Tested with a pair of GSkill F3-1866C9-8GSR. This makes sure in particular that we honor the CMD rate requested by the XMP profile. This memory kit needs a CMD rate of 2 to be stable at DDR3-1600 and up, even though it passes training at 1. Also respect requested CWL to match vendor firmware and for a potential increase in performance. The tested kit requests a tighter value than the per-frequency table provides and has shown to be stable using that setting. Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9 Signed-off-by: Dan Elkouby Reviewed-on: https://review.coreboot.org/25664 Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit_common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/northbridge/intel/sandybridge/raminit_common.h') diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index ab6e592f07..1f32dcddc4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -94,6 +94,8 @@ typedef struct ramctr_timing_st { u32 tWTR; u32 tRTP; u32 tFAW; + u32 tCWL; + u32 tCMD; /* Latencies in terms of clock cycles * They are saved separately as they are needed for DRAM MRS commands*/ u8 CAS; /* CAS read latency */ -- cgit v1.2.3