From 1244f4b52fe423eeac2621672aa1786232f2ca0b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 10 May 2012 11:31:40 -0700 Subject: Rework Sandybridge MRC cache handling - Separate Sandybridge from ChromeOS a bit The Sandybridge code depends on chromeos features a whole lot. As a first step, provide a code path to look up the MRC cache without depending on u-boot. - Move mrc cache handling to separate file This enables us to handle the MRC cache from ramstage, where we can write the flash safely (eg. to update the cache). Also teach it to lookup the current MRC cache from CBMEM, as the original data block isn't available anymore. After all the preparations, finally write to the SPI as necessary. It's a simple round robin wear levelling that erases the entire MRC cache region when it's full and starts from the beginning. Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12 Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/1001 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/northbridge/intel/sandybridge/northbridge.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/northbridge/intel/sandybridge/northbridge.c') diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index b2baaa3d4e..7d7153e73c 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -77,6 +77,12 @@ int add_northbridge_resources(struct lb_memory *mem) return 0; } +void cbmem_post_handling(void); +void cbmem_post_handling(void) +{ + update_mrc_cache(); +} + static int get_pcie_bar(u32 *base, u32 *len) { device_t dev; -- cgit v1.2.3